forked from HEL/circuiteria
88 lines
2.5 KiB
Markdown
88 lines
2.5 KiB
Markdown
# circuiteria
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Circuiteria is a [Typst](https://typst.app) package for drawing block circuit diagrams using the [CeTZ](https://typst.app/universe/package/cetz) package.
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<p align="center">
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<img src="./gallery/platypus.png" alt="A platypus / Perry the Platypus meme made with colored rounded rectangles">
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</p>
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## Examples
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<table>
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<tr>
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<td colspan="2">
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<a href="./gallery/test.typ">
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<img src="./gallery/test.png" width="500px" alt="Block diagram of a multi-cycle RISC-V FPGA processor">
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</a>
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</td>
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</tr>
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<tr>
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<td colspan="2">A bit of everything</td>
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</tr>
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<tr>
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<td colspan="2">
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<a href="./gallery/test5.typ">
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<img src="./gallery/test5.png" width="500px" alt="Block diagram of a single-cycle RISC-V processor">
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</a>
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</td>
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</tr>
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<tr>
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<td colspan="2">Wires everywhere</td>
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</tr>
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<tr>
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<td>
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<a href="./gallery/test4.typ">
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<img src="./gallery/test4.png" width="250px" alt="Top-level block diagram of a single-cycle RISC-V processor">
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</a>
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</td>
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<td>
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<a href="./gallery/test6.typ">
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<img src="./gallery/test6.png" width="250px" alt="Block diagram of a simple single-cycle RISC-V ALU">
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</a>
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</td>
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</tr>
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<tr>
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<td>Groups</td>
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<td>Rotated</td>
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</tr>
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<tr>
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<td colspan="2">
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<a href="./gallery/verilog.typ">
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<img src="./gallery/verilog.png" width="500px" alt="Block automatically generated from a Verilog module">
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</a>
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</td>
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</tr>
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<tr>
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<td colspan="2">Generated from a Verilog module</td>
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</tr>
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</table>
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> **Note**\
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> These circuit layouts were copied from a digital design course given by prof. S. Zahno and recreated using this package
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*Click on the example image to jump to the code.*
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## Usage
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For more information, see the [manual](manual.pdf)
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To use this package, simply import [circuiteria](https://typst.app/universe/package/circuiteria) and call the `circuit` function:
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```typ
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#import "@preview/circuiteria:0.2.1"
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#circuiteria.circuit({
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import circuiteria: *
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...
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})
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```
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### Verilog modules
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Blocks can be generated automatically from Verilog/SystemVerilog sources.
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AXI4, AXI4-Lite, AXI4-Stream and Vivado BRAM interface signals are grouped
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into single bus ports, and clock/reset signals are detected and placed
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together:
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```typ
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#circuiteria.circuit({
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import circuiteria: *
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verilog.block(read("my_module.v"), x: 0, y: 0)
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})
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```
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The port ids are the signal names, or the bus prefixes for inferred buses
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(e.g. `"my_module-port-s_axi"`). |