Klagarge/Cursor
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Rémi Heredero 2021-11-24 10:50:51 +01:00
commit c7ba678fbb
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# Ignore HDL Designer Folder
Prefs/hds_user/logs/
Prefs/dc_user/
Prefs/dp_user/
Prefs/hds.info/
# Ignore HDL Designer Task generated files
Board/concat/concatenated.vhd
Board/concat/eln_cursor.vhd
# Ignore files automatically generated by HDL Designer
.cache.dat
*.bak
*.lck
*.vhd.info
default_view
*_entity.vhd
*_struct.vhd
*_fsm.vhd
*.vhg
*.DS_STORE
*.xrf/
# Ignore verilog and c files
*.v
*.sv
*.svh
*.c
*.cpp
*.psl

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#-------------------------------------------------------------------------------
# Clock, reset
#
NET "clock" LOC = "A10" ;
NET "reset_n" LOC = "A15" | PULLUP ;
NET "testMode" LOC = "T10";
#-------------------------------------------------------------------------------
# Buttons, V1 board
#
#NET "restart_n" LOC = "E8" ;
#NET "go1_n" LOC = "G9" ;
#NET "go2_n" LOC = "F9" ;
#NET "button4_n" LOC = "F7" ;
#-------------------------------------------------------------------------------
# Buttons, V2 board
#
NET "restart_n" LOC = "G9" ;
NET "go1_n" LOC = "F9" ;
NET "go2_n" LOC = "F7" ;
NET "button4_n" LOC = "F8" ;
#-------------------------------------------------------------------------------
# Sensors
#
NET "sensor1_n" LOC = "B6" ;
NET "sensor2_n" LOC = "A6" ;
NET "encoderA_n" LOC = "G4" ;
NET "encoderB_n" LOC = "E2" ;
NET "encoderI_n" LOC = "G3" ;
#-------------------------------------------------------------------------------
# Motor control
#
NET "motorOn" LOC = "B3" ;
NET "side1" LOC = "G6" ;
NET "side2" LOC = "C5" ;
#-------------------------------------------------------------------------------
# LEDs, V1 board
#
#NET "LED1" LOC = "B16";
#NET "LED2" LOC = "A16";
#NET "LEDs_n<1>" LOC = "E7" ;
#NET "LEDs_n<2>" LOC = "B14";
#NET "LEDs_n<3>" LOC = "B13";
#NET "LEDs_n<4>" LOC = "B11";
#NET "LEDs_n<5>" LOC = "A8" ;
#NET "LEDs_n<6>" LOC = "C7" ;
#NET "LEDs_n<7>" LOC = "A14";
#NET "LEDs_n<8>" LOC = "A11";
#-------------------------------------------------------------------------------
# LEDs, V2 board
#
NET "LED1" LOC = "B16";
NET "LED2" LOC = "A16";
NET "LEDs<1>" LOC = "E9" ;
NET "LEDs<2>" LOC = "A8";
NET "LEDs<3>" LOC = "F11";
NET "LEDs<4>" LOC = "B11";
NET "LEDs<5>" LOC = "B13";
NET "LEDs<6>" LOC = "B14";
NET "LEDs<7>" LOC = "E7" ;
NET "LEDs<8>" LOC = "E8" ;
#-------------------------------------------------------------------------------
# LCD
#
NET "LCD_CS1_n" LOC = "A11";
NET "LCD_SCL" LOC = "D7" ;
NET "LCD_SI" LOC = "C7" ;
NET "LCD_A0" LOC = "A14";
NET "LCD_RST_n" LOC = "A13";
#-------------------------------------------------------------------------------
# Globals
#
NET "*" IOSTANDARD = LVCMOS33;

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DIALECT atom VHDL_ANY

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Board/hds/.hdlsidedata/_fpga_cursor_struct.vhg._fpf Normal file
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DIALECT atom VHDL_ANY

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TOP_MARKER atom 1
DEFAULT_ARCHITECTURE atom struct
DEFAULT_FILE atom @f@p@g@a_cursor/struct.bd

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="C:/Users/oliver.gubler/eda/VHDL/labs/ELN_cursor/Board/concat/cursor.vhd" xil_pn:type="FILE_VHDL">
<!--<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>-->
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="C:/Users/oliver.gubler/eda/VHDL/labs/ELN_cursor/Board/concat/cursor.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add File to project" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Pads" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Advanced FSM Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Array Bounds Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Constrain" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Baud rate" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SmartModels (PPC, MGT) Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Powerdown" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
<property xil_pn:name="Convert Tristates To Logic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Default Enum Encoding Goal" xil_pn:value="default" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Bandgap Generator for DCMs to save power" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable I/O insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Display Incremental Messages" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="EDIF" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Enhanced Design Summary" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fanout Guide" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Full Case" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate UCF from RTL Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Clock Delay 0 (Binary String)" xil_pn:value="11111" xil_pn:valueState="default"/>
<property xil_pn:name="Global Clock Delay 1 (Binary String)" xil_pn:value="11111" xil_pn:valueState="default"/>
<property xil_pn:name="Global Clock Delay 2 (Binary String)" xil_pn:value="11111" xil_pn:valueState="default"/>
<property xil_pn:name="Global Clock Delay 3 (Binary String)" xil_pn:value="11111" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="_" xil_pn:valueState="non-default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Start View" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="AbstractSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|FPGA_cursor|struct" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="C:/Users/oliver.gubler/eda/VHDL/labs/ELN_cursor/Board/concat/cursor.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/FPGA_cursor" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Instantiation Template Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Key 1 (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Key 2 (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Key 3 (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Key 4 (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Key 5 (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Load Setting File" xil_pn:value="Default" xil_pn:valueState="non-default"/>
<property xil_pn:name="Load Timing Specification Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Location of Key 0 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Location of Key 1 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Location of Key 2 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Location of Key 3 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Location of Key 4 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Location of Key 5 in Sequence" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Effort Level" xil_pn:value="Standard" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Fit UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Critical Paths" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Critical Paths Synthesis" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Start/End Points" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Summary Paths" xil_pn:value="10" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="-use_new_parser yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Base Name" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="FPGA_cursor" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fg320" xil_pn:valueState="non-default"/>
<property xil_pn:name="Parallel Case" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pipelining" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="FPGA_cursor_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="FPGA_cursor_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="FPGA_cursor_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="FPGA_cursor_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Push Tristates across Process/Block Boundaries" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Release Set/Reset (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="FPGA_cursor" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Clock Frequencies" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Critical Paths" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Report Missing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Timing Summary" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Timing Violations" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Error Report" xil_pn:valueState="non-default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing Precision" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing Synthesis" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Setting Output File" xil_pn:value="Default" xil_pn:valueState="non-default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Show Clock Domain Crossing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Show Net Fan Out" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator Path" xil_pn:value="c:/eda/modelsim/win32" xil_pn:valueState="non-default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Starting CBC Value (Hex)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Key" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Symbolic FSM Compiler" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Sysgen Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Transform Set/Reset on DFFs to Latches" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tri-state Buffer Transformation Mode" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Update modelsim.ini File for Xilinx SmartModel Use" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP48" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Safe FSM" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax Precision" xil_pn:value="VHDL 93" xil_pn:valueState="non-default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Standard" xil_pn:value="Verilog 2001" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Mapped VHDL Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Write Mapped Verilog Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Write Vendor Constraint File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|FPGA_cursor|struct" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="boardTester" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_HdlTemplateLang" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_HdlTemplateName" xil_pn:value="boardTester.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-05-15T11:45:42" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="19D4427DD0AF46549C10BB115F0B7A5B" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_xawInstTempTargetLang" xil_pn:value="VHDL" xil_pn:valueState="default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

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1
Cursor/hds/.hdlsidedata/_cursorcircuit_entity.vhg._fpf Normal file
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DIALECT atom VHDL_2008

1
Cursor/hds/.hdlsidedata/_cursorcircuit_struct.vhg._fpf Normal file
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DIALECT atom VHDL_ANY

1
Cursor/hds/.hdlsidedata/_lcddisplay_entity.vhg._fpf Normal file
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DIALECT atom VHDL_ANY

1
Cursor/hds/.hdlsidedata/_lcddisplay_fsm.vhg._fpf Normal file
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DIALECT atom VHDL_ANY

3
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TOP_MARKER atom 1
DEFAULT_ARCHITECTURE atom studentVersion
DEFAULT_FILE atom cursor@circuit/student@version.bd

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ARCHITECTURE test OF cursor_tester IS
constant clockFrequency: real := 66.0E6;
constant clockPeriod: time := 1.0/clockFrequency * 1 sec;
signal sClock: std_uLogic := '1';
signal testMode_int: std_uLogic;
constant buttonsPulseWidth : time := 100 us;
constant pulsesPerTurn: integer := 2000;
constant pwmReadBitNb: positive :=8;
constant pwmLowpassAddBitNb: positive :=8;
constant voltageToSpeedBitNb: positive := 8;
signal side1Acc: unsigned(pwmReadBitNb+pwmLowpassAddBitNb-1 downto 0) := (others => '0');
signal side2Acc: unsigned(pwmReadBitNb+pwmLowpassAddBitNb-1 downto 0) := (others => '0');
signal side1M: unsigned(pwmReadBitNb-1 downto 0);
signal side2M: unsigned(pwmReadBitNb-1 downto 0);
signal position: signed(pwmReadBitNb+voltageToSpeedBitNb-1 downto 0) := (others => '0');
signal stepCount: unsigned(1 downto 0);
BEGIN
------------------------------------------------------------------------------
-- clock and reset
--
reset <= '1', '0' after 2*clockPeriod;
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after clockPeriod*9/10;
------------------------------------------------------------------------------
-- test sequence
--
process
begin
testMode_int <= '1';
restart <= '0';
go1 <= '0';
go2 <= '0';
button4 <= '0';
sensor1 <= '0';
sensor2 <= '0';
wait for 0.1 ms;
----------------------------------------------------------------------------
-- restart
restart <= '1', '0' after buttonsPulseWidth;
wait for 0.25 ms;
sensor1 <= '1', '0' after buttonsPulseWidth;
wait for 0.25 ms;
----------------------------------------------------------------------------
-- advance to first stop point
go1 <= '1', '0' after buttonsPulseWidth;
wait for 2 ms;
----------------------------------------------------------------------------
-- advance to second stop point
go2 <= '1', '0' after buttonsPulseWidth;
wait for 2 ms;
----------------------------------------------------------------------------
-- go back to first stop point
go1 <= '1', '0' after buttonsPulseWidth;
wait for 2 ms;
----------------------------------------------------------------------------
-- back to start with sensor reset
restart <= '1', '0' after buttonsPulseWidth;
wait for 0.5 ms;
sensor1 <= '1', '0' after buttonsPulseWidth;
wait for 0.5 ms;
----------------------------------------------------------------------------
-- advance to second stop point
go2 <= '1', '0' after buttonsPulseWidth;
wait for 3 ms;
----------------------------------------------------------------------------
-- back to start with counter stop
restart <= '1', '0' after buttonsPulseWidth;
wait for 2 ms;
sensor1 <= '1', '0' after buttonsPulseWidth;
wait for 1 ms;
----------------------------------------------------------------------------
-- quit test mode
testMode_int <= '0';
----------------------------------------------------------------------------
-- advance to first stop point
go1 <= '1', '0' after buttonsPulseWidth;
wait for 2 ms;
wait;
end process;
testMode <= testMode_int;
------------------------------------------------------------------------------
-- PWM lowpass
--
process(sClock)
begin
if rising_edge(sClock) then
if side1 = '1' then
side1Acc <= side1Acc + 2**pwmReadBitNb-1 - shift_right(side1Acc, pwmLowpassAddBitNb);
else
side1Acc <= side1Acc - shift_right(side1Acc, pwmLowpassAddBitNb);
end if;
if side2 = '1' then
side2Acc <= side2Acc + 2**pwmReadBitNb-1 - shift_right(side2Acc, pwmLowpassAddBitNb);
else
side2Acc <= side2Acc - shift_right(side2Acc, pwmLowpassAddBitNb);
end if;
end if;
end process;
side1M <= resize(shift_right(side1Acc, pwmLowpassAddBitNb), side1M'length);
side2M <= resize(shift_right(side2Acc, pwmLowpassAddBitNb), side2M'length);
------------------------------------------------------------------------------
-- motor feedback
--
count: process (sClock)
begin
if motorOn = '1' then
if testMode_int = '0' then
position <= position + to_integer(side1M) - to_integer(side2M);
else
position <= position + (to_integer(side1M) - to_integer(side2M)) * 5;
end if;
end if;
end process count;
stepCount <= resize(shift_right(unsigned(position), position'length-stepCount'length), stepCount'length);
encoderA <= stepCount(1);
encoderB <= not stepCount(1) xor stepCount(0);
encoderI <= '1' when stepCount = pulsesPerTurn-1 else '0';
END ARCHITECTURE test;

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ARCHITECTURE test OF divider_tester IS
constant clockFrequency: real := 66.0E6;
constant clockPeriod: time := 1.0/clockFrequency * 1 sec;
signal sClock: std_uLogic := '1';
BEGIN
reset <= '1', '0' after clockPeriod/4;
sClock <= not sClock after clockPeriod/2;
clock <= sClock after clockPeriod/10;
testMode <= '1', '0' after 10000*clockPeriod;
-- start <= '0',
-- '1' after 210 us,
-- '0' after 210 us + clockPeriod,
-- '1' after 2.1 ms,
-- '0' after 2.1 ms + clockPeriod;
END ARCHITECTURE test;

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--
-- Auto generated dummy architecture for leaf level instance.
--
ARCHITECTURE generatedInstance OF positionCounter_tester IS
BEGIN
END generatedInstance;

1
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1
Cursor_test/hds/.hdlsidedata/_cursor_tb_struct.vhg._fpf Normal file
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DIALECT atom VHDL_ANY

1
Cursor_test/hds/.hdlsidedata/_cursor_tester_entity.vhg._fpf Normal file
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DIALECT atom VHDL_ANY

4
Cursor_test/hds/.hdlsidedata/_cursor_tester_test.vhd._fpf Normal file
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INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_2008

4
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INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_2008

1
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DIALECT atom VHDL_2008

2
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DEFAULT_ARCHITECTURE atom struct
DEFAULT_FILE atom cursor_tb/struct.bd

2
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DEFAULT_ARCHITECTURE atom struct
DEFAULT_FILE atom divider_tb/struct.bd

2
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DEFAULT_ARCHITECTURE atom struct
DEFAULT_FILE atom position@counter_tb/struct.bd

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ARCHITECTURE test OF cursor_tester IS
constant clockPeriod: time := 50 ns;
signal sClock: std_uLogic := '1';
constant pulsesPerTurn: integer := 200;
constant stepPeriodNb: positive := 8;
signal stepEn: std_uLogic := '0';
signal direction: std_uLogic;
signal turning: std_uLogic;
signal stepCount: unsigned(10 downto 0) := (others => '0');
BEGIN
------------------------------------------------------------------------------
-- clock and reset
--
reset <= '1', '0' after clockPeriod/4;
sClock <= not sClock after clockPeriod/2;
clock <= sClock after clockPeriod/10;
------------------------------------------------------------------------------
-- test sequence
--
process
begin
testMode <= '1';
restart <= '0';
go1 <= '0';
go2 <= '0';
setPoint <= '0';
sensor1 <= '0';
sensor2 <= '0';
wait for 1 us;
----------------------------------------------------------------------------
-- advance to first stop point
go1 <= '1', '0' after 1 us;
wait for 4 ms;
----------------------------------------------------------------------------
-- advance to second stop point
go2 <= '1', '0' after 1 us;
wait for 4 ms;
----------------------------------------------------------------------------
-- back to start with sensor reset
restart <= '1', '0' after 1 us;
wait for 0.5 ms;
sensor1 <= '1', '0' after 1 us;
wait for 0.5 ms;
----------------------------------------------------------------------------
-- advance to second stop point
go2 <= '1', '0' after 1 us;
wait for 7 ms;
----------------------------------------------------------------------------
-- go back to first stop point
go1 <= '1', '0' after 1 us;
wait for 4 ms;
----------------------------------------------------------------------------
-- back to start with counter stop
restart <= '1', '0' after 1 us;
wait for 4 ms;
sensor1 <= '1', '0' after 1 us;
wait for 1 ms;
wait;
end process;
------------------------------------------------------------------------------
-- motor feedback
--
turning <= motorOn;
findDirection: process(side1, side2)
begin
if (side1 = '1') and (side2 = '0') then
direction <= '1';
elsif (side1 = '0') and (side2 = '1') then
direction <= '0';
end if;
end process findDirection;
stepEn <= not stepEn after (stepPeriodNb/4)*clockPeriod;
count: process (stepEn)
begin
if turning = '1' then
if direction = '1' then
if stepCount < pulsesPerTurn-1 then
stepCount <= stepCount + 1;
else
stepCount <= to_unsigned(0, stepCount'length);
end if;
else
if stepCount > 0 then
stepCount <= stepCount - 1;
else
stepCount <= to_unsigned(pulsesPerTurn-1, stepCount'length);
end if;
end if;
end if;
end process count;
encoderA <= stepCount(1);
encoderB <= not stepCount(1) xor stepCount(0);
encoderI <= '1' when stepCount = pulsesPerTurn-1 else '0';
END test;

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ARCHITECTURE test OF divider_tester IS
constant clockPeriod: time := 50 ns;
signal sClock: std_uLogic := '1';
BEGIN
reset <= '1', '0' after clockPeriod/4;
sClock <= not sClock after clockPeriod/2;
clock <= sClock after clockPeriod/10;
testMode <= '1', '0' after 10000*clockPeriod;
start <= '0',
'1' after 210 us,
'0' after 210 us + clockPeriod,
'1' after 2.1 ms,
'0' after 2.1 ms + clockPeriod;
END test;

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ARCHITECTURE test OF positionCounter_tester IS
constant clockPeriod: time := 50 ns;
signal sClock: std_uLogic := '1';
constant pulsesPerTurn: integer := 200;
constant stepPeriodNb: positive := 16;
signal stepEn: std_uLogic := '0';
signal direction: std_uLogic;
signal stepCount: unsigned(10 downto 0) := (others => '0');
BEGIN
------------------------------------------------------------------------------
-- clock and reset
--
reset <= '1', '0' after clockPeriod/4;
sClock <= not sClock after clockPeriod/2;
clock <= sClock after clockPeriod/10;
------------------------------------------------------------------------------
-- encoder signals
--
direction <= '1', '0' after 2000*clockPeriod;
stepEn <= not stepEn after (stepPeriodNb/4)*clockPeriod;
count: process (stepEn)
begin
if direction = '1' then
if stepCount < pulsesPerTurn-1 then
stepCount <= stepCount + 1;
else
stepCount <= to_unsigned(0, stepCount'length);
end if;
else
if stepCount > 0 then
stepCount <= stepCount - 1;
else
stepCount <= to_unsigned(pulsesPerTurn-1, stepCount'length);
end if;
end if;
end process count;
encoderA <= stepCount(1);
encoderB <= stepCount(1) xor stepCount(0);
encoderI <= '1' when stepCount = pulsesPerTurn-1 else '0';
------------------------------------------------------------------------------
-- control signals
--
clear <= '0',
'1' after 100*clockPeriod,
'0' after 101*clockPeriod;
END test;

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ARCHITECTURE test OF pulseWidthModulator_tester IS
constant clockPeriod: time := 50 ns;
signal sClock: std_uLogic := '1';
constant enPeriodNb: positive := 3;
signal sEn: std_uLogic := '0';
BEGIN
------------------------------------------------------------------------------
-- clock and reset
--
reset <= '1', '0' after clockPeriod/4;
sClock <= not sClock after clockPeriod/2;
clock <= sClock after clockPeriod/10;
------------------------------------------------------------------------------
-- control signals
--
amplitude <= to_unsigned( 64, amplitude'length),
to_unsigned(128, amplitude'length) after 10*256*enPeriodNb*clockPeriod,
to_unsigned(192, amplitude'length) after 20*256*enPeriodNb*clockPeriod;
sEn <= '1' after (enPeriodNb-1)*clockPeriod when sEn = '0' else '0' after clockPeriod;
en <= sEn;
END test;

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All Rights Reserved
Copyright (c) 2019 - HES-SO Valais Wallis
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.

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-- filename: blinker.vhd
-- kind: vhdl file
-- first created: 18.06.2012
-- created by: zas
--------------------------------------------------------------------------------
-- History:
-- v0.1 : zas 18.06.2012 -- Initial Version
--------------------------------------------------------------------------------
-- Description:
-- For let blinking a LED with an signal event
-- Mode = 0 (reactive on rising edge)
-- ___________________________________________
-- input ____/
-- ___________________
-- output ____/ \_______________________
-- time 0s 0.5s 1s
--
-- _
-- input ____/ \_________________________________________
-- ___________________
-- output ____/ \_______________________
-- time 0s 0.5s 1s
----
-- Mode = 1 (reactive on falling edge)
-- _____
-- input \__________________________________________
-- ___________________
-- output ______/ \_____________________
-- time 0s 0.5s 1s
--
-- _
-- input ____/ \_________________________________________
-- ___________________
-- output ______ / \____________________
-- time 0s 0.5s 1s
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.NUMERIC_STD.all;
LIBRARY Common;
USE Common.CommonLib.all;
ARCHITECTURE arch OF blinker IS
constant c : integer := clockFrequency/2; -- 500ms blink
signal cnt : unsigned(requiredBitNb(c)-1 downto 0);
signal en_delay : std_ulogic;
signal blink_int : std_ulogic;
BEGIN
process(reset, clock)
begin
if reset = '1' then
en_delay <= '0';
blink_int <= '0';
cnt <= (others => '0');
elsif rising_edge(clock) then
en_delay <= en;
-- detect rising_edge
if mode = 0 then
if blink_int = '0' and en_delay = '0' and en = '1' then
blink_int <= '1';
end if;
else
-- detect falling edge
if blink_int = '0' and en_delay = '1' and en = '0' then
blink_int <= '1';
end if;
end if;
-- blink
if blink_int = '1' then
if (cnt < c) then
cnt <= cnt + 1;
else
cnt <= (others => '0');
blink_int <= '0';
end if;
end if;
end if;
end process;
-- Set output
blink <= blink_int;
END ARCHITECTURE arch;

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--------------------------------------------------------------------------------
-- Copyright 2012 HES-SO Valais Wallis (www.hevs.ch)
--------------------------------------------------------------------------------
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program IS distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>
-- -----------------------------------------------------------------------------
-- Common Lib
--
-- -----------------------------------------------------------------------------
-- Authors:
-- cof: [François Corthay](francois.corthay@hevs.ch)
-- guo: [Oliver A. Gubler](oliver.gubler@hevs.ch)
-- -----------------------------------------------------------------------------
-- Changelog:
-- 2016-06 : guo
-- added function sel
-- 2015-06 : guo
-- added counterBitNb
-- added documentation
-- -----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
PACKAGE CommonLib IS
------------------------------------------------------------------------------
-- Returns the number of bits needed to represent the given val
-- Examples:
-- requiredBitNb(1) = 1 (1)
-- requiredBitNb(2) = 2 (10)
-- requiredBitNb(3) = 2 (11)
function requiredBitNb(val : integer) return integer;
------------------------------------------------------------------------------
-- Returns the number of bits needed to count val times (0 to val-1)
-- Examples:
-- counterBitNb(1) = 1 (0)
-- counterBitNb(2) = 1 (0->1)
-- counterBitNb(3) = 2 (0->1->10)
function counterBitNb(val : integer) return integer;
------------------------------------------------------------------------------
-- Functions to return one or the other input based on a boolean.
-- Can be used to build conditional constants.
-- Example:
-- constant bonjour_c : string := sel(ptpRole = master, "fpga20", "fpga02");
function sel(Cond : BOOLEAN; If_True, If_False : integer)
return integer;
function sel(Cond : BOOLEAN; If_True, If_False : string)
return string;
function sel(Cond : BOOLEAN; If_True, If_False : std_ulogic_vector)
return std_ulogic_vector;
function sel(Cond : BOOLEAN; If_True, If_False : unsigned)
return unsigned;
function sel(Cond : BOOLEAN; If_True, If_False : signed)
return signed;
END CommonLib;

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--------------------------------------------------------------------------------
-- Copyright 2012 HES-SO Valais Wallis (www.hevs.ch)
--------------------------------------------------------------------------------
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program IS distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>
-- -----------------------------------------------------------------------------
-- Often used functions
--
-- -----------------------------------------------------------------------------
-- Authors:
-- cof: [François Corthay](francois.corthay@hevs.ch)
-- guo: [Oliver A. Gubler](oliver.gubler@hevs.ch)
-- -----------------------------------------------------------------------------
-- Changelog:
-- 2016-06 : guo
-- added function sel
-- 2015-06 : guo
-- added counterBitNb
-- -----------------------------------------------------------------------------
PACKAGE BODY CommonLib IS
function requiredBitNb (val : integer) return integer is
variable powerOfTwo, bitNb : integer;
begin
powerOfTwo := 1;
bitNb := 0;
while powerOfTwo <= val loop
powerOfTwo := 2 * powerOfTwo;
bitNb := bitNb + 1;
end loop;
return bitNb;
end requiredBitNb;
function counterBitNb (val : integer) return integer is
variable powerOfTwo, bitNb : integer;
begin
powerOfTwo := 1;
bitNb := 0;
while powerOfTwo < val loop
powerOfTwo := 2 * powerOfTwo;
bitNb := bitNb + 1;
end loop;
return bitNb;
end counterBitNb;
function sel(Cond : BOOLEAN; If_True, If_False : integer)
return integer is
begin
if (Cond = TRUE) then
return (If_True);
else
return (If_False);
end if;
end function sel;
function sel(Cond : BOOLEAN; If_True, If_False : string)
return string is
begin
if (Cond = TRUE) then
return (If_True);
else
return (If_False);
end if;
end function sel;
function sel(Cond : BOOLEAN; If_True, If_False : std_ulogic_vector)
return std_ulogic_vector is
begin
if (Cond = TRUE) then
return (If_True);
else
return (If_False);
end if;
end function sel;
function sel(Cond : BOOLEAN; If_True, If_False : unsigned)
return unsigned is
begin
if (Cond = TRUE) then
return (If_True);
else
return (If_False);
end if;
end function sel;
function sel(Cond : BOOLEAN; If_True, If_False : signed)
return signed is
begin
if (Cond = TRUE) then
return (If_True);
else
return (If_False);
end if;
end function sel;
END CommonLib;

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-- filename: debouncer.vhd
-- kind: vhdl file
-- first created: 05.03.2012
-- created by: zas
--------------------------------------------------------------------------------
-- History:
-- v0.1 : zas 05.03.2012 -- Initial Version
-- v0.2 : cof 22.01.2013 -- synchronization to clock
--------------------------------------------------------------------------------
-- Description:
-- Debounces a button on both edges.
-- _ _ ____________________ _ _
-- input ____/ \_/ \_/ \_/ \_/ \______
-- _____________________________
-- output _____/ \____________
--
--------------------------------------------------------------------------------
ARCHITECTURE rtl OF debouncerULogicVector IS
signal inputNormal : std_ulogic_vector(input'range);
signal inputSynch, inputDelayed, inputChanged : std_ulogic;
signal debounceCounter : unsigned(counterBitNb-1 downto 0);
BEGIN
------------------------------------------------------------------------------
-- adapt polarity
adaptPolarity: process(input)
begin
for index in input'range loop
inputNormal(index) <= input(index) xor invertInput;
end loop;
end process adaptPolarity;
------------------------------------------------------------------------------
-- Synchronize input to clock
synchInput: process(reset, clock)
variable inputOr : std_ulogic;
begin
if reset = '1' then
inputSynch <= '0';
elsif rising_edge(clock) then
inputOr := '0';
for index in input'range loop
inputOr := inputOr or inputNormal(index);
end loop;
inputSynch <= inputOr;
end if;
end process synchInput;
------------------------------------------------------------------------------
-- Find edge on input
delayInput: process(reset, clock)
begin
if reset = '1' then
inputDelayed <= '0';
elsif rising_edge(clock) then
inputDelayed <= inputSynch;
end if;
end process delayInput;
inputChanged <= '1' when inputDelayed /= inputSynch
else '0';
------------------------------------------------------------------------------
-- Debounce counter
countDeadTime: process(reset, clock)
begin
if reset = '1' then
debounceCounter <= (others => '0');
elsif rising_edge(clock) then
if debounceCounter = 0 then
if inputChanged = '1' then
debounceCounter <= debounceCounter - 1;
end if;
else
debounceCounter <= debounceCounter - 1;
end if;
end if;
end process countDeadTime;
------------------------------------------------------------------------------
-- Update output
updateOutput: process(reset, clock)
begin
if reset = '1' then
debounced <= (others => '0');
elsif rising_edge(clock) then
if (inputChanged = '1') and (debounceCounter = 0) then
debounced <= inputNormal;
elsif debounceCounter = 1 then
debounced <= inputNormal;
end if;
end if;
end process updateOutput;
END ARCHITECTURE rtl;

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-- filename: debouncer.vhd
-- kind: vhdl file
-- first created: 05.03.2012
-- created by: zas
--------------------------------------------------------------------------------
-- History:
-- v0.1 : zas 05.03.2012 -- Initial Version
-- v0.2 : cof 22.01.2013 -- synchronization to clock
-- -- direct reaction on both edges
--------------------------------------------------------------------------------
-- Description:
-- Debounces a button on both edges.
-- _ _ ____________________ _ _
-- input ____/ \_/ \_/ \_/ \_/ \______
-- _____________________________
-- output _____/ \____________
--
--------------------------------------------------------------------------------
ARCHITECTURE rtl OF debouncer IS
signal debounceCounter : unsigned(counterBitNb-1 downto 0);
signal inputSynch, inputDelayed, inputChanged : std_ulogic;
BEGIN
------------------------------------------------------------------------------
-- Synchronize input to clock
synchInput: process(reset, clock)
begin
if reset = '1' then
inputSynch <= '0';
elsif rising_edge(clock) then
inputSynch <= input xor invertInput;
end if;
end process synchInput;
------------------------------------------------------------------------------
-- Find edge on input
delayInput: process(reset, clock)
begin
if reset = '1' then
inputDelayed <= '0';
elsif rising_edge(clock) then
inputDelayed <= inputSynch;
end if;
end process delayInput;
inputChanged <= '1' when inputDelayed /= inputSynch
else '0';
------------------------------------------------------------------------------
-- Debounce counter
countDeadTime: process(reset, clock)
begin
if reset = '1' then
debounceCounter <= (others => '0');
elsif rising_edge(clock) then
if debounceCounter = 0 then
if inputChanged = '1' then
debounceCounter <= debounceCounter - 1;
end if;
else
debounceCounter <= debounceCounter - 1;
end if;
end if;
end process countDeadTime;
------------------------------------------------------------------------------
-- Update output
updateOutput: process(reset, clock)
begin
if reset = '1' then
debounced <= '0';
elsif rising_edge(clock) then
if (inputChanged = '1') and (debounceCounter = 0) then
debounced <= input;
elsif debounceCounter = 1 then
debounced <= input;
end if;
end if;
end process updateOutput;
END ARCHITECTURE rtl;

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--------------------------------------------------------------------------------
-- Copyright 2014 HES-SO Valais Wallis (www.hevs.ch)
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program IS distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
-- EdgeDetector
-- Detect rising and falling edges of a signal.
--
--------------------------------------------------------------------------------
-- History:
-- v0.1 : guo 2014-04-02 -- Initial version
-- v1.0 : cof 2019-10-02 -- Updated symbol
--------------------------------------------------------------------------------
ARCHITECTURE RTL OF edgeDetector IS
SIGNAL pulse_delayed : std_ulogic;
SIGNAL rising_detected_s : std_ulogic;
SIGNAL falling_detected_s : std_ulogic;
BEGIN
-- delay pulse
reg : PROCESS (reset, clock)
BEGIN
IF reset = '1' THEN
pulse_delayed <= '0';
ELSIF rising_edge(clock) THEN
pulse_delayed <= pulse;
END IF;
END PROCESS reg ;
-- edge detection
rising <= '1' when (pulse = '1') and (pulse_delayed = '0')
else '0';
falling <= '1' when (pulse = '0') and (pulse_delayed = '1')
else '0';
END ARCHITECTURE RTL;

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ARCHITECTURE rtl OF rotaryToUnsigned IS
signal rotaryDelayed1, rotaryDelayed2, rotaryStable : unsigned(rotary'range);
signal rotary_changed : std_ulogic;
signal glitchDelayCounter : unsigned(counterBitNb-1 downto 0);
signal rotaryStableDelayed : unsigned(rotary'range);
signal numberMsbs : unsigned(number'length-rotary'length-1 downto 0);
BEGIN
------------------------------------------------------------------------------
-- synchronize input and detect changes
delayRotary: process(reset, clock)
begin
if reset = '1' then
rotaryDelayed1 <= (others => '0');
rotaryDelayed2 <= (others => '0');
elsif rising_edge(clock) then
rotaryDelayed1 <= rotary;
rotaryDelayed2 <= rotaryDelayed1;
end if;
end process delayRotary;
rotary_changed <= '1' when rotaryDelayed1 /= rotaryDelayed2
else '0';
-- count dead time
countDeadTime: process(reset, clock)
begin
if reset = '1' then
glitchDelayCounter <= (others => '1');
elsif rising_edge(clock) then
if rotary_changed = '1' then
glitchDelayCounter <= (others => '1');
elsif glitchDelayCounter > 0 then
glitchDelayCounter <= glitchDelayCounter - 1;
end if;
end if;
end process countDeadTime;
-- store new rotary button value
storeRotary: process(reset, clock)
begin
if reset = '1' then
rotaryStable <= (others => '0');
elsif rising_edge(clock) then
if glitchDelayCounter = 0 then
rotaryStable <= rotaryDelayed2;
end if;
end if;
end process storeRotary;
------------------------------------------------------------------------------
-- keep previous value of stablilzed rotary
delayRotaryStable: process(reset, clock)
begin
if reset = '1' then
rotaryStableDelayed <= (others => '0');
elsif rising_edge(clock) then
rotaryStableDelayed <= rotaryStable;
end if;
end process delayRotaryStable;
-- synchronize input and detect changes
updateMsbs: process(reset, clock)
begin
if reset = '1' then
numberMsbs <= (others => '0');
elsif rising_edge(clock) then
if (rotaryStable = 0) and (rotaryStableDelayed+1 = 0) then
numberMsbs <= numberMsbs + 1;
elsif (rotaryStable+1 = 0) and (rotaryStableDelayed = 0) then
numberMsbs <= numberMsbs - 1;
end if;
end if;
end process updateMsbs;
number <= numberMsbs & rotaryStableDelayed;
END ARCHITECTURE rtl;

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--------------------------------------------------------------------------------
-- Description:
-- Filters short time spikes.
-- _ _ ____________________ _ _
-- input ____/ \_/ \_/ \_/ \_/ \_________________
-- _____________________________
-- output ________________/ \____________
--
--------------------------------------------------------------------------------
ARCHITECTURE rtl OF spikeFilter IS
signal filterCounter : unsigned(counterBitNb-1 downto 0);
signal inputSynch, inputDelayed, inputChanged : std_ulogic;
BEGIN
------------------------------------------------------------------------------
-- Synchronize input to clock
synchInput: process(reset, clock)
begin
if reset = '1' then
inputSynch <= '0';
elsif rising_edge(clock) then
inputSynch <= input xor invertInput;
end if;
end process synchInput;
------------------------------------------------------------------------------
-- Find edge on input
delayInput: process(reset, clock)
begin
if reset = '1' then
inputDelayed <= '0';
elsif rising_edge(clock) then
inputDelayed <= inputSynch;
end if;
end process delayInput;
inputChanged <= '1' when inputDelayed /= inputSynch
else '0';
------------------------------------------------------------------------------
-- Debounce counter
countDeadTime: process(reset, clock)
begin
if reset = '1' then
filterCounter <= (others => '0');
elsif rising_edge(clock) then
if filterCounter = 0 then
if inputChanged = '1' then
filterCounter <= filterCounter + 1;
end if;
elsif signed(filterCounter)+1 = 0 then
if inputChanged = '1' then
filterCounter <= filterCounter - 1;
end if;
else
if inputSynch = '0' then
filterCounter <= filterCounter - 1;
else
filterCounter <= filterCounter + 1;
end if;
end if;
end if;
end process countDeadTime;
------------------------------------------------------------------------------
-- Update output
updateOutput: process(reset, clock)
begin
if reset = '1' then
filtered <= '0';
elsif rising_edge(clock) then
if filterCounter = 0 then
filtered <= '0';
elsif signed(filterCounter)+1 = 0 then
filtered <= '1';
end if;
end if;
end process updateOutput;
END ARCHITECTURE rtl;

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-- filename: toggler.vhd
-- kind: vhdl file
-- first created: 05.03.2012
-- created by: zas
--------------------------------------------------------------------------------
-- History:
-- v0.1 : cof 22.01.2013 -- Initial version
--------------------------------------------------------------------------------
-- Description:
-- Debounces a button on both edges.
-- _ _
-- input ____/ \__________________________/ \____________
-- _____________________________
-- output _____/ \____________
--
-- If the generic "counterBitNb" is greater than zero, a debouncer is placed on
-- the input signal.
--
--------------------------------------------------------------------------------
ARCHITECTURE rtl OF toggler IS
signal inputDebounced : std_ulogic;
signal inputDelayed, inputChangedTo1 : std_ulogic;
signal toggle_int : std_ulogic;
COMPONENT debouncer
GENERIC (
counterBitNb : positive := 18;
invertInput : std_ulogic := '0'
);
PORT (
reset : IN std_ulogic ;
clock : IN std_ulogic ;
input : IN std_ulogic ;
debounced : OUT std_ulogic
);
END COMPONENT;
BEGIN
------------------------------------------------------------------------------
-- Debounce input
useInputDirectly: if counterBitNb = 0 generate
inputDebounced <= input;
end generate useInputDirectly;
debounceInput: if counterBitNb > 0 generate
I_debouncer : debouncer
GENERIC MAP (
counterBitNb => counterBitNb,
invertInput => invertInput
)
PORT MAP (
reset => reset,
clock => clock,
input => input,
debounced => inputDebounced
);
end generate debounceInput;
------------------------------------------------------------------------------
-- Find edge on input
delayInput: process(reset, clock)
begin
if reset = '1' then
inputDelayed <= '0';
elsif rising_edge(clock) then
inputDelayed <= inputDebounced;
end if;
end process delayInput;
inputChangedTo1 <= '1' when (inputDebounced = '1') and (inputDelayed = '0')
else '0';
------------------------------------------------------------------------------
-- Toggle output
toggleOutput: process(reset, clock)
begin
if reset = '1' then
toggle_int <= '0';
elsif rising_edge(clock) then
if inputChangedTo1 = '1' then
toggle_int <= not toggle_int;
end if;
end if;
end process toggleOutput;
toggle <= toggle_int;
END ARCHITECTURE rtl;

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INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_2008

1
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INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_2002

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1
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1
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1
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DIALECT atom VHDL_2008

1
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DIALECT atom VHDL_2008

1
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DIALECT atom VHDL_2008

1
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DIALECT atom VHDL_2008

1
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1
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DEFAULT_ARCHITECTURE atom arch
DEFAULT_FILE atom blinker_arch.vhd

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DEFAULT_ARCHITECTURE atom rtl
DEFAULT_FILE atom debounce_rtl.vhd

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DEFAULT_FILE atom debouncer_RTL.vhd
DEFAULT_ARCHITECTURE atom rtl

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DEFAULT_ARCHITECTURE atom RTL
DEFAULT_FILE atom edgeDetector_rtl.vhd

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DEFAULT_FILE atom rotaryToUnsigned_rtl.vhd
DEFAULT_ARCHITECTURE atom rtl

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DEFAULT_FILE atom toggler_RTL.vhd
DEFAULT_ARCHITECTURE atom rtl

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ARCHITECTURE sim OF clockGenerator IS
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
signal clock_int: std_uLogic := '1';
BEGIN
reset <= '1', '0' after 2*clockPeriod;
clock_int <= not clock_int after clockPeriod/2;
clock <= transport clock_int after clockPeriod*9.0/10.0;
END ARCHITECTURE sim;

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LIBRARY Common;
USE Common.commonLib.all;
LIBRARY Common_test;
USE Common_test.testUtils.all;
ARCHITECTURE test OF commonLib_tb IS
constant maxPowOf2: positive := 10;
constant indent: string(1 to 2) := (others => ' ');
BEGIN
process
variable value, bitNb: positive;
BEGIN
print("testing function " & '"' & "requiredBitNb" & '"');
for index in 1 to maxPowOf2 loop
for offset in -1 to 1 loop
value := 2**index + offset;
bitNb := requiredBitNb(value);
print(indent & "requiredBitNb(" & sprintf("%d", value) & ") = " & sprintf("%d", bitNb));
end loop;
print("");
end loop;
wait;
end process;
END ARCHITECTURE test;

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ARCHITECTURE RTL OF debouncerULogicVector_tester IS
constant clockFrequency : real := 100.0E6;
constant clockPeriod : time := 1.0/clockFrequency * 1 sec;
signal clock_int : std_ulogic := '1';
constant longDelay : time := 2**(counterBitNb+1) * clockPeriod;
BEGIN
------------------------------------------------------------------------------
-- reset and clock
reset <= '1', '0' after 3*clockPeriod;
clock_int <= not clock_int after clockPeriod/2;
clock <= transport clock_int after clockPeriod*9/10;
------------------------------------------------------------------------------
-- input signal
process
begin
input <= (others => '0');
wait for longDelay;
-- transition 0 to 1
input(1) <= '1',
'0' after 1*clockPeriod,
'1' after 3*clockPeriod,
'0' after 5*clockPeriod,
'1' after 6*clockPeriod,
'0' after 8*clockPeriod,
'1' after 10*clockPeriod;
wait for longDelay;
-- transition to other bit
-- transition 1 to 0
input(1) <= '0';
wait for longDelay;
input(2) <= '1';
wait for longDelay;
-- transition 1 to 0
input(2) <= '0',
'1' after 1*clockPeriod,
'0' after 3*clockPeriod,
'1' after 5*clockPeriod,
'0' after 6*clockPeriod,
'1' after 8*clockPeriod,
'0' after 10*clockPeriod;
wait for longDelay;
-- short 1 pulse
input(3) <= '1',
'0' after 1*clockPeriod,
'1' after 3*clockPeriod,
'0' after 5*clockPeriod,
'1' after 6*clockPeriod,
'0' after 8*clockPeriod;
-- end of simulation
wait;
end process;
END ARCHITECTURE RTL;

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ARCHITECTURE test OF debouncer_tester IS
constant clockFrequency : real := 66.0E6;
constant clockPeriod : time := 1.0/clockFrequency * 1 sec;
signal clock_int : std_ulogic := '1';
BEGIN
------------------------------------------------------------------------------
-- reset and clock
reset <= '1', '0' after 3*clockPeriod;
clock_int <= not clock_int after clockPeriod/2;
clock <= transport clock_int after clockPeriod*9/10;
------------------------------------------------------------------------------
-- input signal
process
begin
input <= '0';
wait for 10*clockPeriod;
-- transition 0 to 1
input <= '1',
'0' after 1*clockPeriod,
'1' after 3*clockPeriod,
'0' after 5*clockPeriod,
'1' after 6*clockPeriod,
'0' after 8*clockPeriod,
'1' after 10*clockPeriod;
wait for 50*clockPeriod;
-- transition 1 to 0
input <= '0',
'1' after 1*clockPeriod,
'0' after 3*clockPeriod,
'1' after 5*clockPeriod,
'0' after 6*clockPeriod,
'1' after 8*clockPeriod,
'0' after 10*clockPeriod;
wait for 50*clockPeriod;
-- short 1 pulse
input <= '1',
'0' after 1*clockPeriod,
'1' after 3*clockPeriod,
'0' after 5*clockPeriod,
'1' after 6*clockPeriod,
'0' after 8*clockPeriod;
-- end of simulation
wait;
end process;
END ARCHITECTURE test;

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# testing function "requiredBitNb"
# requiredBitNb(1) = 1
# requiredBitNb(2) = 2
# requiredBitNb(3) = 2
#
# requiredBitNb(3) = 2
# requiredBitNb(4) = 3
# requiredBitNb(5) = 3
#
# requiredBitNb(7) = 3
# requiredBitNb(8) = 4
# requiredBitNb(9) = 4
#
# requiredBitNb(15) = 4
# requiredBitNb(16) = 5
# requiredBitNb(17) = 5
#
# requiredBitNb(31) = 5
# requiredBitNb(32) = 6
# requiredBitNb(33) = 6
#
# requiredBitNb(63) = 6
# requiredBitNb(64) = 7
# requiredBitNb(65) = 7
#
# requiredBitNb(127) = 7
# requiredBitNb(128) = 8
# requiredBitNb(129) = 8
#
# requiredBitNb(255) = 8
# requiredBitNb(256) = 9
# requiredBitNb(257) = 9
#
# requiredBitNb(511) = 9
# requiredBitNb(512) = 10
# requiredBitNb(513) = 10
#
# requiredBitNb(1023) = 10
# requiredBitNb(1024) = 11
# requiredBitNb(1025) = 11

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ARCHITECTURE test OF rotaryToUnsigned_tester IS
constant clockFrequency : real := 100.0E6;
constant clockPeriod : time := 1.0/clockFrequency * 1 sec;
signal clock_int : std_ulogic := '1';
constant stepPeriod : time := 100*clockPeriod;
signal rotary_int : unsigned(rotary'range);
BEGIN
------------------------------------------------------------------------------
-- reset and clock
reset <= '1', '0' after 3*clockPeriod;
clock_int <= not clock_int after clockPeriod/2;
clock <= transport clock_int after clockPeriod*9/10;
------------------------------------------------------------------------------
-- input signal
turnRotary: process
begin
rotary_int <= (others => '0');
wait for 10*stepPeriod;
-- count over max value
for index in 1 to 2**outputBitNb+2 loop
rotary_int <= rotary_int + 1;
wait for stepPeriod;
end loop;
-- count down again
for index in 1 to 2**outputBitNb+2 loop
rotary_int <= rotary_int - 1;
wait for stepPeriod;
end loop;
-- end of simulation
wait;
end process turnRotary;
addGlitches: process
begin
wait on rotary_int;
rotary <= (others => '0');
wait for clockPeriod;
rotary <= (others => '1');
wait for clockPeriod;
rotary <= rotary_int;
end process addGlitches;
END ARCHITECTURE test;

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ARCHITECTURE test OF spikeFilter_tester IS
constant clockFrequency : real := 100.0E6;
constant clockPeriod : time := 1.0/clockFrequency * 1 sec;
signal clock_int : std_ulogic := '1';
BEGIN
------------------------------------------------------------------------------
-- reset and clock
reset <= '1', '0' after 3*clockPeriod;
clock_int <= not clock_int after clockPeriod/2;
clock <= transport clock_int after clockPeriod*9/10;
------------------------------------------------------------------------------
-- input signal
process
begin
input <= '0';
wait for 10*clockPeriod;
-- loop on pulse width
for pulseWidth in 1 to 10 loop
-- send positive pulses train
for index in 1 to 8 loop
input <= '1';
wait for pulseWidth * clockPeriod;
input <= '0';
wait for pulseWidth * clockPeriod;
end loop;
-- set input high
input <= '1';
wait for 100*clockPeriod;
-- send negative pulses train
for index in 1 to 8 loop
input <= '0';
wait for pulseWidth * clockPeriod;
input <= '1';
wait for pulseWidth * clockPeriod;
end loop;
-- set input low
input <= '0';
wait for 100*clockPeriod;
end loop;
-- end of simulation
wait;
end process;
END ARCHITECTURE test;

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LIBRARY std;
USE std.textio.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
PACKAGE testUtils IS
--============================================================================
-- console output
--
procedure print(value : string);
--============================================================================
-- string manipulation
--
-- conversion to lowercase
function lc(value : string) return string;
procedure lc(value : inout line);
-- conversion to uppercase
function uc(value : string) return string;
procedure uc(value : inout line);
-- expand a string to a given length
function pad(
value : string;
string_length : natural;
fill_char : character := ' ';
right_justify : boolean := false
) return string;
-- remove separator characters at beginning and end of line
procedure rm_side_separators(
value : inout line;
separators : in string
);
procedure rm_side_separators(
value : inout line
);
-- remove multiple occurences of separator characters
procedure trim_line(
value : inout line;
separators : in string
);
procedure trim_line(
value : inout line
);
-- remove all occurences of separator characters
procedure rm_all_separators(
value : inout line;
separators : in string
);
procedure rm_all_separators(
value : inout line
);
-- find and remove first word
procedure read_first(
value : inout line;
separators : in string;
first : out line
);
procedure read_first(
value : inout line;
first : out line
);
-- find and remove last word
procedure read_last(
value : inout line;
separators : in string;
last : out line
);
procedure read_last(
value : inout line;
last : out line
);
--============================================================================
-- formatted string output
--
-- format codes:
-- code integer real std_logic std_(u)logic_vector (un)signed time
-- b v v v v binary
-- c character
-- d v v v v v decimal
-- e real numbers, with power of 10 exponent
-- f v v fixed point real numbers
-- s string
-- ts v time in seconds
-- tm v time in milliseconds
-- tu v time in microseconds
-- tn v time in nanoseconds
-- tp v time in picoseconds
-- x v v v v hexadecimal
-- X v v v v hexadecimal with upper-case letters
function sprintf(format : string; value : integer ) return string;
function sprintf(format : string; value : real ) return string;
function sprintf(format : string; value : std_logic ) return string;
function sprintf(format : string; value : std_ulogic_vector) return string;
function sprintf(format : string; value : std_logic_vector ) return string;
function sprintf(format : string; value : unsigned ) return string;
function sprintf(format : string; value : signed ) return string;
function sprintf(format : string; value : time ) return string;
--============================================================================
-- formatted string input
--
subtype nibbleUlogicType is std_ulogic_vector(3 downto 0);
subtype nibbleUnsignedType is unsigned(3 downto 0);
function sscanf(value : character) return natural;
function sscanf(value : character) return nibbleUlogicType;
function sscanf(value : character) return nibbleUnsignedType;
function sscanf(value : string ) return natural;
function sscanf(value : string ) return unsigned;
function sscanf(value : string ) return std_ulogic_vector;
function sscanf(value : string ) return time;
procedure sscanf(value : inout line; time_val : out time);
END testUtils;

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PACKAGE BODY testUtils IS
--============================================================================
-- console output
--
procedure print(value : string) is
variable my_line : line;
begin
write(my_line, value);
writeLine(output, my_line);
deallocate(my_line);
end print;
--============================================================================
-- string manipulation
--
------------------------------------------------------------------------------
-- change to lowercase
------------------------------------------------------------------------------
procedure lc(value: inout line) is
variable out_line: line;
begin
for index in value'range loop
if (value(index) >= 'A') and (value(index) <= 'Z') then
value(index) := character'val(character'pos(value(index))
- character'pos('A')
+ character'pos('a')
);
end if;
end loop;
end lc;
function lc(value: string) return string is
variable out_line: line;
begin
write(out_line, value);
lc(out_line);
return(out_line.all);
end lc;
------------------------------------------------------------------------------
-- change to uppercase
------------------------------------------------------------------------------
procedure uc(value: inout line) is
variable out_line: line;
begin
for index in value'range loop
if (value(index) >= 'a') and (value(index) <= 'z') then
value(index) := character'val(character'pos(value(index))
- character'pos('a')
+ character'pos('A')
);
end if;
end loop;
end uc;
function uc(value: string) return string is
variable out_line: line;
begin
write(out_line, value);
uc(out_line);
return(out_line.all);
end uc;
------------------------------------------------------------------------------
-- formatted string output: padding and justifying
------------------------------------------------------------------------------
function pad(
value : string;
string_length : natural;
fill_char : character := ' ';
right_justify : boolean := false
) return string is
variable value_line : line;
variable out_line : line;
variable value_length : natural;
variable shift_sign : boolean;
begin
write(value_line, value);
value_length := value_line.all'length;
if string_length = 0 then
write(out_line, value_line.all);
elsif string_length > value_length then
if right_justify then
if (value_line.all(value_line.all'left) <= '-') and not(fill_char = ' ') then
shift_sign := true;
write(out_line, value_line.all(value_line.all'left));
end if;
for index in 1 to string_length-value_length loop
write(out_line, fill_char);
end loop;
end if;
if shift_sign then
write(out_line, value_line.all(value_line.all'left+1 to value_line.all'right));
else
write(out_line, value_line.all);
end if;
if not right_justify then
for index in 1 to string_length-value_length loop
write(out_line, fill_char);
end loop;
end if;
elsif string_length < value_length then
write(out_line, '#');
write(out_line, value_line.all(value_length-string_length+2 to value_length));
else
write(out_line, value_line.all);
end if;
deallocate(value_line);
return(out_line.all);
end pad;
------------------------------------------------------------------------------
-- remove separator characters at beginning and end of line
------------------------------------------------------------------------------
procedure rm_side_separators(
value : inout line;
separators : in string
) is
variable input_line : line := value;
variable found : boolean := false;
variable position : integer := 0;
begin
-- remove all separators in the beginning
position := -1;
for character_index in input_line'range loop
found := false;
for separator_index in separators'range loop
if input_line(character_index) = separators(separator_index) then
found := true;
end if;
end loop;
if found then
position := character_index;
else
exit;
end if;
end loop;
if position > -1 then
input_line := new string'( input_line(position+1 to input_line'right) );
end if;
-- remove all separators in the end
position := -1;
for character_index in input_line'reverse_range loop
found := false;
for separator_index in separators'range loop
if input_line(character_index) = separators(separator_index) then
found := true;
end if;
end loop;
if found then
position := character_index;
else
exit;
end if;
end loop;
if position > -1 then
input_line := new string'( input_line(input_line'left to position-1) );
end if;
value := input_line;
end;
procedure rm_side_separators(value : inout line) is
begin
rm_side_separators(value, " :" & ht);
end;
------------------------------------------------------------------------------
-- remove multiple occurences of separator characters, keeping one single
------------------------------------------------------------------------------
procedure trim_line(
value : inout line;
separators : in string
) is
variable input_line: line := value;
variable output_line: line := new string'("");
variable is_separator, was_separator : boolean := false;
begin
rm_side_separators(input_line);
for character_index in input_line'range loop
is_separator := false;
for separator_index in separators'range loop
if input_line.all(character_index) = separators(separator_index) then
is_separator := true;
end if;
end loop;
if not (is_separator and was_separator) then
write(output_line, input_line.all(character_index));
end if;
was_separator := is_separator;
end loop;
value := output_line;
end;
procedure trim_line(value : inout line) is
begin
trim_line(value, " :" & ht);
end;
------------------------------------------------------------------------------
-- remove all occurences of separator characters
------------------------------------------------------------------------------
procedure rm_all_separators(
value : inout line;
separators : in string
) is
variable input_line : line := value;
variable is_separator : boolean := false;
begin
-- remove separators from beginn and end of the line
-- rm_separator_be(value, separators);
-- empty output line
value := new string'("");
-- find all separator symbols
for character_index in input_line'range loop
is_separator := false;
for separator_index in separators'range loop
if input_line(character_index) = separators(separator_index) then
is_separator := true;
end if;
end loop;
if not is_separator then
write(value, input_line.all(character_index));
end if;
end loop;
end;
procedure rm_all_separators(value : inout line) is
begin
rm_all_separators(value, " _." & ht);
end;
------------------------------------------------------------------------------
-- read first "word" out of a line
------------------------------------------------------------------------------
procedure read_first(
value : inout line;
separators : in string;
first : out line
) is
variable input_line: line;
variable position: natural := 0;
begin
input_line := value;
for character_index in input_line.all'reverse_range loop
for separator_index in separators'range loop
if input_line.all(character_index) = separators(separator_index) then
position := character_index;
end if;
end loop;
end loop;
if position > 1 then
first := new string'(input_line.all(input_line'left to position-1));
value := new string'(input_line(position+1 to input_line'right));
else
first := new string'(input_line.all);
value := new string'("");
end if;
end;
procedure read_first(value : inout line; first : out line) is
begin
read_first(value, " :" & ht, first);
end;
------------------------------------------------------------------------------
-- read last "word" out of a line
------------------------------------------------------------------------------
procedure read_last(
value : inout line;
separators : in string;
last : out line
) is
variable input_line: line := value;
variable position: natural := 0;
begin
for character_index in input_line'range loop
for separator_index in separators'range loop
if input_line(character_index) = separators(separator_index) then
position := character_index;
end if;
end loop;
end loop;
if position <= input_line'right and
position > 0 then
value := new string'(input_line(input_line'left to position-1));
last := new string'(input_line(position+1 to input_line'right));
else
last := new string'(input_line.all);
end if;
end;
procedure read_last(value : inout line; last : out line) is
begin
read_last(value, " :" & ht, last);
end;
--============================================================================
-- formatted string output, internal functions
--
------------------------------------------------------------------------------
-- get format specification
------------------------------------------------------------------------------
procedure get_format_items(
format : string;
right_justify : out boolean;
add_sign : out boolean;
fill_char : out character;
total_length : out natural;
point_precision : out natural;
format_type : inout line
) is
variable find_sign : boolean := false;
variable find_padding : boolean := false;
variable find_length : boolean := false;
variable find_precision : boolean := false;
variable find_type : boolean := false;
variable right_justify_int : boolean := true;
variable total_length_int : natural := 0;
variable point_precision_int : natural := 0;
begin
add_sign := false;
fill_char := ' ';
for index in 1 to format'length loop
if find_type then
write(format_type, format(index));
end if;
if find_precision then
if (format(index) >= '0') and (format(index) <= '9') then
point_precision_int := 10*point_precision_int + character'pos(format(index)) - character'pos('0');
if format(index+1) >= 'A' then
find_precision := false;
find_type := true;
end if;
end if;
end if;
if find_length then
if (format(index) >= '0') and (format(index) <= '9') then
total_length_int := 10*total_length_int + character'pos(format(index)) - character'pos('0');
end if;
if format(index) = '.' then
find_length := false;
find_precision := true;
elsif format(index+1) >= 'A' then
find_length := false;
find_type := true;
end if;
end if;
if find_padding then
if format(index) = '0' then
if right_justify_int then
fill_char := '0';
end if;
end if;
find_padding := false;
if format(index+1) >= 'A' then
find_type := true;
else
find_length := true;
end if;
end if;
if find_sign then
if format(index) = '-' then
right_justify_int := false;
end if;
if format(index) = '+' then
add_sign := true;
end if;
find_sign := false;
if format(index+1) <= '-' then
find_sign := true;
elsif format(index+1) = '0' then
find_padding := true;
elsif format(index+1) >= 'A' then
find_type := true;
else
find_length := true;
end if;
end if;
if format(index) = '%' then
if format(index+1) <= '-' then
find_sign := true;
elsif format(index+1) = '0' then
find_padding := true;
elsif format(index+1) >= 'A' then
find_type := true;
else
find_length := true;
end if;
end if;
end loop;
right_justify := right_justify_int;
total_length := total_length_int;
point_precision := point_precision_int;
end get_format_items;
------------------------------------------------------------------------------
-- formatted string output: converting std_ulogic to character
------------------------------------------------------------------------------
function to_character(value: std_ulogic) return character is
variable out_value: character;
begin
case value is
when 'U' => out_value := 'U';
when 'X' => out_value := 'X';
when '0' => out_value := '0';
when '1' => out_value := '1';
when 'Z' => out_value := 'Z';
when 'W' => out_value := 'W';
when 'L' => out_value := 'L';
when 'H' => out_value := 'H';
when '-' => out_value := '-';
end case;
return(out_value);
end to_character;
------------------------------------------------------------------------------
-- formatted string output: binary integer
------------------------------------------------------------------------------
function sprintf_b(value: std_ulogic_vector) return string is
variable out_line : line;
begin
for index in value'range loop
write(out_line, to_character(value(index)));
end loop;
return(out_line.all);
end sprintf_b;
------------------------------------------------------------------------------
-- formatted string output: decimal integer
------------------------------------------------------------------------------
function sprintf_d(
right_justify : boolean;
add_sign : boolean;
fill_char : character;
string_length : natural;
value : integer
) return string is
variable value_line : line;
begin
if add_sign and (value >= 0) then
write(value_line, '+');
end if;
write(value_line, value);
if string_length = 0 then
return(value_line.all);
else
return(pad(value_line.all, string_length, fill_char, right_justify));
end if;
end sprintf_d;
------------------------------------------------------------------------------
-- formatted string output: fixed point real
------------------------------------------------------------------------------
function sprintf_f(
right_justify : boolean;
add_sign : boolean;
fill_char : character;
string_length : natural;
point_precision : natural;
value : real
) return string is
variable point_precision_int : natural;
variable integer_part : integer;
variable decimal_part : natural;
variable value_line : line;
begin
if point_precision = 0 then
point_precision_int := 6;
else
point_precision_int := point_precision;
end if;
if value >= 0.0 then
integer_part := integer(value-0.5);
else
integer_part := - integer(-value-0.5);
end if;
decimal_part := abs(integer((value-real(integer_part))*(10.0**point_precision_int)));
if add_sign and (value >= 0.0) then
write(value_line, '+');
end if;
write(value_line, integer_part);
write(value_line, '.');
write(value_line, sprintf_d(true, false, '0', point_precision_int, decimal_part));
if string_length = 0 then
return(value_line.all);
else
return(pad(value_line.all, string_length, fill_char, right_justify));
end if;
end sprintf_f;
------------------------------------------------------------------------------
-- formatted string output: hexadecimal integer
------------------------------------------------------------------------------
function sprintf_X(
extend_unsigned : boolean;
value : std_ulogic_vector
) return string is
variable bit_count : positive;
variable value_line : line;
variable out_line : line;
variable nibble: string(1 to 4);
begin
bit_count := value'length;
while (bit_count mod 4) /= 0 loop
if extend_unsigned then
write(value_line, to_character('0'));
else
write(value_line, to_character(value(value'high)));
end if;
bit_count := bit_count + 1;
end loop;
write(value_line, sprintf_b(value));
for index in value_line.all'range loop
if (index mod 4) = 0 then
nibble := value_line.all(index-3 to index);
case nibble is
when "0000" => write(out_line, 0);
when "0001" => write(out_line, 1);
when "0010" => write(out_line, 2);
when "0011" => write(out_line, 3);
when "0100" => write(out_line, 4);
when "0101" => write(out_line, 5);
when "0110" => write(out_line, 6);
when "0111" => write(out_line, 7);
when "1000" => write(out_line, 8);
when "1001" => write(out_line, 9);
when "1010" => write(out_line, 'A');
when "1011" => write(out_line, 'B');
when "1100" => write(out_line, 'C');
when "1101" => write(out_line, 'D');
when "1110" => write(out_line, 'E');
when "1111" => write(out_line, 'F');
when others => write(out_line, 'X');
end case;
end if;
end loop;
return(out_line.all);
end sprintf_X;
--============================================================================
-- formatted string output, interface functions
--
------------------------------------------------------------------------------
-- integer
------------------------------------------------------------------------------
function sprintf(format : string; value : integer) return string is
variable right_justify : boolean;
variable add_sign : boolean;
variable fill_char : character;
variable string_length : natural;
variable point_precision : natural;
variable format_type : line;
begin
get_format_items(format, right_justify, add_sign, fill_char,
string_length, point_precision, format_type);
if format_type.all = "b" then
if string_length = 0 then
string_length := 8;
end if;
return(sprintf_b(std_ulogic_vector(to_signed(value, string_length+1)(string_length-1 downto 0))));
elsif format_type.all = "d" then
return(sprintf_d(right_justify, add_sign, fill_char, string_length, value));
elsif format_type.all = "f" then
return(sprintf_f(right_justify, add_sign, fill_char,
string_length, point_precision, real(value)));
elsif (format_type.all = "X") or (format_type.all = "x") then
if string_length = 0 then
string_length := 8;
end if;
string_length := 4*string_length;
if format_type.all = "X" then
return(sprintf_X(false, std_ulogic_vector(to_signed(value, string_length+1)(string_length-1 downto 0))));
else
return(lc(sprintf_X(false, std_ulogic_vector(to_signed(value, string_length+1)(string_length-1 downto 0)))));
end if;
else
return("Unhandled format type: '" & format_type.all & "'");
end if;
end sprintf;
------------------------------------------------------------------------------
-- real
------------------------------------------------------------------------------
function sprintf(format : string; value : real) return string is
variable right_justify : boolean;
variable add_sign : boolean;
variable fill_char : character;
variable string_length : natural;
variable point_precision : natural;
variable format_type : line;
begin
get_format_items(format, right_justify, add_sign, fill_char,
string_length, point_precision, format_type);
if (format_type.all = "d") or (point_precision = 0) then
return(sprintf_d(right_justify, add_sign, fill_char,
string_length, integer(value)));
elsif format_type.all = "f" then
return(sprintf_f(right_justify, add_sign, fill_char,
string_length, point_precision, value));
else
return("Unhandled format type: '" & format_type.all & "'");
end if;
end sprintf;
------------------------------------------------------------------------------
-- std_logic
------------------------------------------------------------------------------
function sprintf(format : string; value : std_logic) return string is
variable right_justify : boolean;
variable add_sign : boolean;
variable fill_char : character;
variable string_length : natural;
variable point_precision : natural;
variable format_type : line;
variable logic_vector: std_logic_vector(1 to 1);
begin
get_format_items(format, right_justify, add_sign, fill_char,
string_length, point_precision, format_type);
if (format_type.all = "b") or (format_type.all = "d") or
(format_type.all = "X") or (format_type.all = "x") then
logic_vector(1) := value;
return(sprintf(format, std_ulogic_vector(logic_vector)));
else
return("Not a std_logic format: '" & format_type.all & "'");
end if;
end sprintf;
------------------------------------------------------------------------------
-- std_ulogic_vector
------------------------------------------------------------------------------
function sprintf(format : string; value : std_ulogic_vector) return string is
variable right_justify : boolean;
variable add_sign : boolean;
variable fill_char : character;
variable bit_string_length : natural;
variable point_precision : natural;
variable format_type : line;
begin
get_format_items(format, right_justify, add_sign, fill_char,
bit_string_length, point_precision, format_type);
if format_type.all = "b" then
return(pad(sprintf_b(value), bit_string_length, fill_char, right_justify));
elsif format_type.all = "d" then
return(sprintf_d(right_justify, add_sign, fill_char, bit_string_length, to_integer(unsigned(value))));
elsif (format_type.all = "X") or (format_type.all = "x") then
if format_type.all = "X" then
return(pad(sprintf_X(true, value), bit_string_length, fill_char, right_justify));
else
return(lc(pad(sprintf_X(true, value), bit_string_length, fill_char, right_justify)));
end if;
else
return("Not a std_ulogic_vector format: '" & format_type.all & "'");
end if;
end sprintf;
------------------------------------------------------------------------------
-- std_logic_vector
------------------------------------------------------------------------------
function sprintf(format : string; value : std_logic_vector) return string is
variable right_justify : boolean;
variable add_sign : boolean;
variable fill_char : character;
variable string_length : natural;
variable point_precision : natural;
variable format_type : line;
begin
get_format_items(format, right_justify, add_sign, fill_char,
string_length, point_precision, format_type);
if (format_type.all = "b") or (format_type.all = "d") or
(format_type.all = "X") or (format_type.all = "x") then
return(sprintf(format, std_ulogic_vector(value)));
else
return("Not a std_logic_vector format: '" & format_type.all & "'");
end if;
end sprintf;
------------------------------------------------------------------------------
-- unsigned
------------------------------------------------------------------------------
function sprintf(format : string; value : unsigned) return string is
variable right_justify : boolean;
variable add_sign : boolean;
variable fill_char : character;
variable string_length : natural;
variable point_precision : natural;
variable format_type : line;
begin
get_format_items(format, right_justify, add_sign, fill_char,
string_length, point_precision, format_type);
if (format_type.all = "b") or (format_type.all = "d") or
(format_type.all = "X") or (format_type.all = "x") then
return(sprintf(format, std_ulogic_vector(value)));
else
return("Not an unsigned format: '" & format_type.all & "'");
end if;
end sprintf;
------------------------------------------------------------------------------
-- signed
------------------------------------------------------------------------------
function sprintf(format : string; value : signed) return string is
variable right_justify : boolean;
variable add_sign : boolean;
variable fill_char : character;
variable bit_string_length : natural;
variable point_precision : natural;
variable format_type : line;
begin
get_format_items(format, right_justify, add_sign, fill_char,
bit_string_length, point_precision, format_type);
if (fill_char = '0') and (value(value'left) = '1') then
fill_char := '1';
end if;
if format_type.all = "b" then
return(pad(sprintf_b(std_ulogic_vector(value)), bit_string_length, fill_char, right_justify));
elsif format_type.all = "d" then
return(sprintf_d(right_justify, add_sign, fill_char, bit_string_length, to_integer(signed(value))));
elsif (format_type.all = "X") or (format_type.all = "x") then
if fill_char = '1' then
fill_char := 'F';
end if;
if format_type.all = "X" then
return(pad(sprintf_X(true, std_ulogic_vector(value)), bit_string_length, fill_char, right_justify));
else
return(lc(pad(sprintf_X(true, std_ulogic_vector(value)), bit_string_length, fill_char, right_justify)));
end if;
else
return("Not a signed format: '" & format_type.all & "'");
end if;
end sprintf;
------------------------------------------------------------------------------
-- time
------------------------------------------------------------------------------
function sprintf(format : string; value : time) return string is
variable right_justify : boolean;
variable add_sign : boolean;
variable fill_char : character;
variable string_length : natural;
variable point_precision : natural;
variable format_type : line;
variable scaling : real;
variable base_time : time;
variable unit : string(1 to 3);
begin
get_format_items(format, right_justify, add_sign, fill_char,
string_length, point_precision, format_type);
if format_type.all(format_type.all'left) = 't' then
scaling := 10.0**point_precision;
if format_type.all = "tp" then
base_time := 1 ps;
unit := " ps";
elsif format_type.all = "tn" then
base_time := 1 ns;
unit := " ns";
elsif format_type.all = "tu" then
base_time := 1 us;
unit := " us";
elsif format_type.all = "tm" then
base_time := 1 ms;
unit := " ms";
elsif format_type.all = "ts" then
base_time := 1 sec;
unit := " s.";
else
return("Undefined time format: '" & format_type.all & "'");
end if;
if point_precision = 0 then
return(sprintf_d(right_justify, add_sign, fill_char,
string_length, value/base_time) & unit);
else
return(sprintf_f(right_justify, add_sign, fill_char, string_length,
point_precision, real(scaling*value/base_time)/scaling) & unit);
end if;
else
return("Not a time format: '" & format_type.all & "'");
end if;
end sprintf;
--============================================================================
-- formatted string input
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- read a nibble out of a character
------------------------------------------------------------------------------
function sscanf(value : character) return natural is
begin
if (value >= '0') and (value <= '9') then
return(character'pos(value) - character'pos('0'));
elsif (value >= 'a') and (value <= 'f') then
return(character'pos(value) - character'pos('a') + 10);
elsif (value >= 'A') and (value <= 'F') then
return(character'pos(value) - character'pos('A') + 10);
else
return(0);
end if;
end sscanf;
function sscanf(value : character) return nibbleUnsignedType is
begin
return(to_unsigned(sscanf(value), nibbleUnsignedType'length));
end sscanf;
function sscanf(value : character) return nibbleUlogicType is
variable unsigned_value : nibbleUnsignedType;
begin
unsigned_value := sscanf(value);
return(std_ulogic_vector(unsigned_value));
end sscanf;
------------------------------------------------------------------------------
-- read an binary word out of a string
------------------------------------------------------------------------------
function sscanf(value : string) return natural is
variable integer_value : natural;
begin
integer_value := 0;
for index in value'left to value'right loop
integer_value := integer_value*16 + sscanf(value(index));
end loop;
return(integer_value);
end;
function sscanf(value : string) return unsigned is
variable unsigned_value : unsigned(4*value'length-1 downto 0);
begin
unsigned_value := to_unsigned(0,unsigned_value'length);
for index in value'left to value'right loop
unsigned_value := shift_left(unsigned_value,4) + to_unsigned(sscanf(value(index)),4);
end loop;
return(unsigned_value);
end;
function sscanf(value : string) return std_ulogic_vector is
variable unsigned_value : unsigned(4*value'length-1 downto 0);
begin
unsigned_value := sscanf(value);
return(std_ulogic_vector(unsigned_value));
end;
------------------------------------------------------------------------------
-- read time from a string
-- time can be formated as follows:
-- "1ps" or "1 ps" or " 1 ps " or " 1ps"
-- possible time units are: hr, min, sec, ms, us, ns, ps, fs
------------------------------------------------------------------------------
procedure sscanf(
value : inout line;
time_val : out time
) is
variable time_line : line := value;
variable time_base : string(1 to 3);
variable time_value : integer;
variable time_int : time;
begin
-- remove all spaces and tabs
rm_all_separators(time_line);
-- strip time base (3 last characters)
time_base := time_line(time_line'right-2 to time_line'right);
-- separate time value and base
if time_base(2 to 3) = "hr" then
time_int := 1 hr;
time_value := integer'value(time_line(time_line'left to time_line'right -2));
elsif time_base = "min" then
time_int := 1 min;
time_value := integer'value(time_line(time_line'left to time_line'right -3));
elsif time_base = "sec" then
time_int := 1 sec;
time_value := integer'value(time_line(time_line'left to time_line'right -3));
elsif time_base(2 to 3) = "ms" then
time_int := 1 ms;
time_value := integer'value(time_line(time_line'left to time_line'right -2));
elsif time_base(2 to 3) = "us" then
time_int := 1 us;
time_value := integer'value(time_line(time_line'left to time_line'right -2));
elsif time_base(2 to 3) = "ns" then
time_int := 1 ns;
time_value := integer'value(time_line(time_line'left to time_line'right -2));
elsif time_base(2 to 3) = "ps" then
time_int := 1 ps;
time_value := integer'value(time_line(time_line'left to time_line'right -2));
elsif time_base(2 to 3) = "fs" then
time_int := 1 fs;
time_value := integer'value(time_line(time_line'left to time_line'right -2));
else
time_int := 0 ps;
time_value := 1;
end if;
-- build time from value and base
time_val := time_int * time_value;
end;
function sscanf(value : string) return time is
variable value_line : line;
variable time_val : time;
begin
value_line := new string'(value);
sscanf(value_line, time_val);
return(time_val);
end;
END testUtils;

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