exercice 3

VHD_test/hdl/tb_24_1_3_entity.vhd

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+-- VHDL Entity VHD_test.tb_24_1_3.symbol
+--
+-- Created:
+--          by - remy.borgeat.UNKNOWN (WE10993)
+--          at - 15:01:24 20.03.2024
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+
+
+ENTITY tb_24_1_3 IS
+-- Declarations
+
+END tb_24_1_3 ;
+

VHD_test/hdl/tb_24_1_3_struct.vhd

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+--
+-- VHDL Architecture VHD_test.tb_24_1_3.struct
+--
+-- Created:
+--          by - remi.heredero.UNKNOWN (WE2330808)
+--          at - 13:45:47 22.03.2024
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+LIBRARY VHD;
+
+ARCHITECTURE struct OF tb_24_1_3 IS
+
+   -- Architecture declarations
+   constant positionBitNb : positive := 8;
+   
+   constant clockFrequency : real := 100.0E6;
+   constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
+   signal sClock :  std_uLogic := '1';
+   
+   signal position_int : integer := 0;
+
+   -- Internal signal declarations
+   SIGNAL clock    : std_ulogic;
+   SIGNAL pwmEn    : std_ulogic;
+   SIGNAL reset    : std_ulogic;
+   SIGNAL testMode : std_ulogic;
+
+
+   -- Component Declarations
+   COMPONENT ex_24_1_3
+   GENERIC (
+      timerBitNb    : positive := 8;
+      testModeBitNb : positive := 1
+   );
+   PORT (
+      testMode : IN     std_ulogic ;
+      clock    : IN     std_ulogic ;
+      reset    : IN     std_ulogic ;
+      pwmEn    : OUT    std_ulogic 
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : ex_24_1_3 USE ENTITY VHD.ex_24_1_3;
+   -- pragma synthesis_on
+
+
+BEGIN
+   -- Architecture concurrent statements
+   -- HDL Embedded Text Block 1 eb1
+   reset <= '1', '0' after 2*clockPeriod;
+   sClock <= not sClock after clockPeriod/2;
+   clock <= transport sClock after clockPeriod*9/10;
+   
+   testMode <= '1', '0' after 100*clockPeriod;
+
+
+   -- Instance port mappings.
+   I_dut : ex_24_1_3
+      GENERIC MAP (
+         timerBitNb    => 14,
+         testModeBitNb => 1
+      )
+      PORT MAP (
+         testMode => testMode,
+         clock    => clock,
+         reset    => reset,
+         pwmEn    => pwmEn
+      );
+
+END struct;