exercice 4

VHD/hdl/ex_24_1_4_entity.vhd

@@ -0,0 +1,26 @@
+-- VHDL Entity VHD.ex_24_1_4.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 12:57:27 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY ex_24_1_4 IS
+   PORT( 
+      A     : IN     std_ulogic;
+      B     : IN     std_ulogic;
+      clock : IN     std_ulogic;
+      reset : IN     std_ulogic;
+      en    : OUT    std_ulogic;
+      dir   : OUT    std_ulogic
+   );
+
+-- Declarations
+
+END ex_24_1_4 ;
+

VHD/hdl/ex_24_1_4_studentVersion.vhd

@@ -1,5 +1,52 @@
 architecture studentVersion of ex_24_1_4 is
+
+  signal oldA: std_ulogic;
+  signal oldB: std_ulogic;
+
 begin
-  en <= '0';
-  dir <= '0';
+
+  process(reset, clock) begin
+    if reset = '1' then 
+      en <= '0';
+      dir <= '0';
+      oldA <= '0';
+      oldA <= '0';
+    elsif rising_edge(clock) then 
+      oldA <= a;
+      oldB <= b;
+
+      if (a='1' and oldA='0') then
+        en <= '1';
+        if b = '0' then
+          dir <= '1';
+        else 
+          dir <= '0';
+        end if;
+      elsif (b='1' and oldB='0') then
+        en <= '1';
+        if a = '0' then
+          dir <= '0';
+        else 
+          dir <= '1';
+        end if;
+      elsif (a='0' and oldA='1') then
+        en <= '1';
+        if b = '1' then
+          dir <= '1';
+        else 
+          dir <= '0';
+        end if;
+      elsif (b='0' and oldB='1') then
+        en <= '1';
+        if a = '1' then
+          dir <= '0';
+        else 
+          dir <= '1';
+        end if;
+      else
+        en <= '0';
+      end if;
+    end if;
+  end process;
+
 end studentVersion;