Initial commit

VHD/hdl/ex_24_1_1_entity.vhd

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+-- VHDL Entity VHD.ex_24_1_1.symbol
+--
+-- Created:
+--          by - remy.borgeat.UNKNOWN (WE10993)
+--          at - 15:02:45 20.03.2024
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY ex_24_1_1 IS
+   GENERIC( 
+      counterBitNb : positive := 8
+   );
+   PORT( 
+      en       : IN     std_ulogic;
+      position : OUT    unsigned (counterBitNb-1 DOWNTO 0);
+      up_down  : IN     std_ulogic;
+      clock    : IN     std_ulogic;
+      reset    : IN     std_ulogic
+   );
+
+-- Declarations
+
+END ex_24_1_1 ;
+

VHD/hdl/ex_24_1_1_studentVersion.vhd

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+architecture studentVersion of ex_24_1_1 is
+
+  signal counter : unsigned(counterBitNb-1 downto 0);
+
+begin
+
+  process(clock, reset) begin
+    if reset = '1' then 
+      counter <= (others => '0');
+    elsif rising_edge(clock) then 
+      if en = '1' then
+        if up_down = '1' then
+          counter <= counter + 1;
+        else
+          counter <= counter -1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  position <= counter;
+end studentVersion;

VHD/hdl/ex_24_1_2_entity.vhd

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+-- VHDL Entity VHD.ex_24_1_2.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 09:18:55 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY ex_24_1_2 IS
+   PORT( 
+      motorOn    : IN     std_ulogic;
+      side1      : OUT    std_ulogic;
+      right_left : IN     std_ulogic;
+      pwm        : IN     std_ulogic;
+      side2      : OUT    std_ulogic
+   );
+
+-- Declarations
+
+END ex_24_1_2 ;
+

VHD/hdl/ex_24_1_2_studentVersion.vhd

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+architecture studentVersion of ex_24_1_2 is
+
+  signal mySignal: std_ulogic;
+
+begin
+
+  process(motorOn, pwm) begin
+    if motorOn = '1' then
+      mySignal <= pwm;
+    else
+      mySignal <= '0';
+    end if;
+  end process;
+
+  process(mySignal, right_left) begin
+    if right_left = '1' then
+      side1 <= mySignal;
+      side2 <= '0';
+    else
+      side1 <= '0';
+      side2 <= mySignal;
+    end if;
+  end process;
+
+end studentVersion;

VHD/hdl/ex_24_1_3_entity.vhg

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+-- VHDL Entity VHD.ex_19_1_3.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 09:40:30 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY ex_19_1_3 IS
+   GENERIC( 
+      timerBitNb    : positive := 8;
+      testModeBitNb : positive := 1
+   );
+   PORT( 
+      testMode : IN     std_ulogic;
+      clock    : IN     std_ulogic;
+      reset    : IN     std_ulogic;
+      pwmEn    : OUT    std_ulogic
+   );
+
+-- Declarations
+
+END ex_19_1_3 ;
+

VHD/hdl/ex_24_1_3_studentVersion.vhd

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+architecture studentVersion of ex_24_1_3 is
+begin
+  pwmEn <= '0';
+end studentVersion;

VHD/hdl/ex_24_1_4_entity.vhg

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+-- VHDL Entity VHD.ex_19_1_4.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 12:57:27 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY ex_19_1_4 IS
+   PORT( 
+      A     : IN     std_ulogic;
+      B     : IN     std_ulogic;
+      clock : IN     std_ulogic;
+      reset : IN     std_ulogic;
+      en    : OUT    std_ulogic;
+      dir   : OUT    std_ulogic
+   );
+
+-- Declarations
+
+END ex_19_1_4 ;
+

VHD/hdl/ex_24_1_4_studentVersion.vhd

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+architecture studentVersion of ex_24_1_4 is
+begin
+  en <= '0';
+  dir <= '0';
+end studentVersion;

VHD/hdl/ex_24_1_5_entity.vhg

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+-- VHDL Entity VHD.ex_19_1_5.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:07:26 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY ex_19_1_5 IS
+   GENERIC( 
+      speedBitNb : positive
+   );
+   PORT( 
+      start : IN     std_ulogic;
+      clock : IN     std_ulogic;
+      reset : IN     std_ulogic;
+      done  : OUT    std_ulogic;
+      speed : OUT    unsigned (speedBitNb-1 DOWNTO 0)
+   );
+
+-- Declarations
+
+END ex_19_1_5 ;
+

VHD/hdl/ex_24_1_5_studentVersion.vhd

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+architecture studentVersion of ex_24_1_5 is
+begin
+  speed <= (others => '0');
+  done <= '0';
+end studentVersion;

VHD/hdl/utils_pkg.vhd

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+PACKAGE utils IS
+
+  function requiredBitNb (val : integer) return integer;
+
+END utils;

VHD/hdl/utils_pkg_body.vhd

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+PACKAGE BODY utils IS
+
+  function requiredBitNb (val : integer) return integer is
+    variable powerOfTwo, bitNb : integer;
+  begin
+    powerOfTwo := 1;
+    bitNb := 0;
+    while powerOfTwo <= val loop
+      powerOfTwo := 2 * powerOfTwo;
+      bitNb := bitNb + 1;
+    end loop;
+    return bitNb;
+  end requiredBitNb;
+
+END utils;