Initial commit

VHD_test/hdl/tb_24_1_1_entity.vhd

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+-- VHDL Entity VHD_test.tb_24_1_1.symbol
+--
+-- Created:
+--          by - remy.borgeat.UNKNOWN (WE10993)
+--          at - 15:01:25 20.03.2024
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+
+
+ENTITY tb_24_1_1 IS
+-- Declarations
+
+END tb_24_1_1 ;
+

VHD_test/hdl/tb_24_1_1_struct.vhd

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+--
+-- VHDL Architecture VHD_test.tb_24_1_1.struct
+--
+-- Created:
+--          by - remy.borgeat.UNKNOWN (WE10993)
+--          at - 15:02:54 20.03.2024
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+LIBRARY VHD;
+
+ARCHITECTURE struct OF tb_24_1_1 IS
+
+   -- Architecture declarations
+   constant positionBitNb : positive := 8;
+   
+   constant clockFrequency : real := 100.0E6;
+   constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
+   signal sClock :  std_uLogic := '1';
+   
+   signal position_int : integer := 0;
+
+   -- Internal signal declarations
+   SIGNAL clock    : std_ulogic;
+   SIGNAL en       : std_ulogic;
+   SIGNAL position : unsigned(positionBitNb-1 DOWNTO 0);
+   SIGNAL reset    : std_ulogic;
+   SIGNAL up_down  : std_ulogic;
+
+
+   -- Component Declarations
+   COMPONENT ex_24_1_1
+   GENERIC (
+      counterBitNb : positive := 8
+   );
+   PORT (
+      en       : IN     std_ulogic ;
+      position : OUT    unsigned (counterBitNb-1 DOWNTO 0);
+      up_down  : IN     std_ulogic ;
+      clock    : IN     std_ulogic ;
+      reset    : IN     std_ulogic 
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : ex_24_1_1 USE ENTITY VHD.ex_24_1_1;
+   -- pragma synthesis_on
+
+
+BEGIN
+   -- Architecture concurrent statements
+   -- HDL Embedded Text Block 1 eb1
+   reset <= '1', '0' after 2*clockPeriod;
+   sClock <= not sClock after clockPeriod/2;
+   clock <= transport sClock after clockPeriod*9/10;
+   
+   process
+     constant stepDelay: time := 1 us;
+   begin
+     en <= '0';
+     up_down <= '1';
+     wait for stepDelay;
+     for index in 0 to 10 loop
+     	en <= '1', '0' after clockPeriod;
+       position_int <= position_int + 1;
+       wait for stepDelay;
+     end loop;
+     up_down <= '0';
+     for index in 10 downto 0 loop
+       en <= '1', '0' after clockPeriod;
+       position_int <= position_int - 1;
+       wait for stepDelay;
+     end loop;
+     wait;
+   end process;
+
+
+   -- Instance port mappings.
+   I_dut : ex_24_1_1
+      GENERIC MAP (
+         counterBitNb => positionBitNb
+      )
+      PORT MAP (
+         en       => en,
+         position => position,
+         up_down  => up_down,
+         clock    => clock,
+         reset    => reset
+      );
+
+END struct;

VHD_test/hdl/tb_24_1_2_entity.vhd

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+-- VHDL Entity VHD_test.tb_24_1_2.symbol
+--
+-- Created:
+--          by - remy.borgeat.UNKNOWN (WE10993)
+--          at - 15:01:24 20.03.2024
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+
+
+ENTITY tb_24_1_2 IS
+-- Declarations
+
+END tb_24_1_2 ;
+

VHD_test/hdl/tb_24_1_2_struct.vhd

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+--
+-- VHDL Architecture VHD_test.tb_24_1_2.struct
+--
+-- Created:
+--          by - remy.borgeat.UNKNOWN (WE10993)
+--          at - 15:01:25 20.03.2024
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+LIBRARY VHD;
+
+ARCHITECTURE struct OF tb_24_1_2 IS
+
+   -- Architecture declarations
+   constant pwmFrequency : real := 1.0E6;
+   constant pwmPeriod : time := (1.0/pwmFrequency) * 1 sec;
+   signal sPwm :  std_uLogic := '1';
+
+   -- Internal signal declarations
+   SIGNAL motorOn    : std_ulogic;
+   SIGNAL pwm        : std_ulogic;
+   SIGNAL right_left : std_ulogic;
+   SIGNAL side1      : std_ulogic;
+   SIGNAL side2      : std_ulogic;
+
+
+   -- Component Declarations
+   COMPONENT ex_24_1_2
+   PORT (
+      motorOn    : IN     std_ulogic ;
+      side1      : OUT    std_ulogic ;
+      right_left : IN     std_ulogic ;
+      pwm        : IN     std_ulogic ;
+      side2      : OUT    std_ulogic 
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : ex_24_1_2 USE ENTITY VHD.ex_24_1_2;
+   -- pragma synthesis_on
+
+
+BEGIN
+   -- Architecture concurrent statements
+   -- HDL Embedded Text Block 1 eb1
+   sPwm <= not sPwm after pwmPeriod/2;
+   pwm <= sPwm;
+   
+   process
+     constant testDelay: time := 10 us;
+   begin
+     motorOn <= '0';
+     right_left <= '1';
+     wait for testDelay;
+   
+     motorOn <= '1';
+     wait for testDelay;
+   
+     right_left <= '0';
+     wait for testDelay;
+   
+     motorOn <= '0';
+     wait for testDelay;
+   
+     wait;
+   end process;
+   
+
+
+   -- Instance port mappings.
+   I_dut : ex_24_1_2
+      PORT MAP (
+         motorOn    => motorOn,
+         side1      => side1,
+         right_left => right_left,
+         pwm        => pwm,
+         side2      => side2
+      );
+
+END struct;

VHD_test/hdl/tb_24_1_3_entity.vhg

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+-- VHDL Entity VHD_test.tb_19_1_3.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 09:36:25 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
+--
+
+
+ENTITY tb_19_1_3 IS
+-- Declarations
+
+END tb_19_1_3 ;
+

VHD_test/hdl/tb_24_1_3_struct.vhg

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+--
+-- VHDL Architecture VHD_test.tb_19_1_3.struct
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 12:43:24 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+LIBRARY VHD;
+
+ARCHITECTURE struct OF tb_19_1_3 IS
+
+   -- Architecture declarations
+   constant positionBitNb : positive := 8;
+   
+   constant clockFrequency : real := 100.0E6;
+   constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
+   signal sClock :  std_uLogic := '1';
+   
+   signal position_int : integer := 0;
+
+   -- Internal signal declarations
+   SIGNAL clock    : std_ulogic;
+   SIGNAL pwmEn    : std_ulogic;
+   SIGNAL reset    : std_ulogic;
+   SIGNAL testMode : std_ulogic;
+
+
+   -- Component Declarations
+   COMPONENT ex_19_1_3
+   GENERIC (
+      timerBitNb    : positive := 8;
+      testModeBitNb : positive := 1
+   );
+   PORT (
+      testMode : IN     std_ulogic ;
+      clock    : IN     std_ulogic ;
+      reset    : IN     std_ulogic ;
+      pwmEn    : OUT    std_ulogic 
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : ex_19_1_3 USE ENTITY VHD.ex_19_1_3;
+   -- pragma synthesis_on
+
+
+BEGIN
+   -- Architecture concurrent statements
+   -- HDL Embedded Text Block 1 eb1
+   reset <= '1', '0' after 2*clockPeriod;
+   sClock <= not sClock after clockPeriod/2;
+   clock <= transport sClock after clockPeriod*9/10;
+   
+   testMode <= '1', '0' after 100*clockPeriod;
+
+
+   -- Instance port mappings.
+   I_dut : ex_19_1_3
+      GENERIC MAP (
+         timerBitNb    => 8,
+         testModeBitNb => 1
+      )
+      PORT MAP (
+         testMode => testMode,
+         clock    => clock,
+         reset    => reset,
+         pwmEn    => pwmEn
+      );
+
+END struct;

VHD_test/hdl/tb_24_1_4_entity.vhg

@@ -0,0 +1,15 @@
+-- VHDL Entity VHD_test.tb_19_1_4.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 12:48:46 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
+--
+
+
+ENTITY tb_19_1_4 IS
+-- Declarations
+
+END tb_19_1_4 ;
+

VHD_test/hdl/tb_24_1_4_struct.vhg

@@ -0,0 +1,101 @@
+--
+-- VHDL Architecture VHD_test.tb_19_1_4.struct
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 12:59:54 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+LIBRARY VHD;
+
+ARCHITECTURE struct OF tb_19_1_4 IS
+
+   -- Architecture declarations
+   constant positionBitNb : positive := 8;
+   
+   constant clockFrequency : real := 100.0E6;
+   constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
+   signal sClock :  std_uLogic := '1';
+   
+   signal position_int : integer := 0;
+
+   -- Internal signal declarations
+   SIGNAL A     : std_ulogic;
+   SIGNAL B     : std_ulogic;
+   SIGNAL clock : std_ulogic;
+   SIGNAL dir   : std_ulogic;
+   SIGNAL en    : std_ulogic;
+   SIGNAL reset : std_ulogic;
+
+
+   -- Component Declarations
+   COMPONENT ex_19_1_4
+   PORT (
+      A     : IN     std_ulogic ;
+      B     : IN     std_ulogic ;
+      clock : IN     std_ulogic ;
+      reset : IN     std_ulogic ;
+      en    : OUT    std_ulogic ;
+      dir   : OUT    std_ulogic 
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : ex_19_1_4 USE ENTITY VHD.ex_19_1_4;
+   -- pragma synthesis_on
+
+
+BEGIN
+   -- Architecture concurrent statements
+   -- HDL Embedded Text Block 1 eb1
+   reset <= '1', '0' after 2*clockPeriod;
+   sClock <= not sClock after clockPeriod/2;
+   clock <= transport sClock after clockPeriod*9/10;
+   
+   process
+     constant stepDelay: time := 1 us;
+   begin
+     wait for stepDelay;
+     for index in 0 to 10 loop
+       position_int <= position_int + 1;
+       wait for stepDelay;
+     end loop;
+     for index in 10 downto 0 loop
+       position_int <= position_int - 1;
+       wait for stepDelay;
+     end loop;
+     wait;
+   end process;
+   
+   process(position_int)
+   begin
+     case to_integer(to_unsigned(position_int, 2)) is
+       when 0 => A <= '0'; B <= '0';
+       when 1 => A <= '1'; B <= '0';
+       when 2 => A <= '1'; B <= '1';
+       when 3 => A <= '0'; B <= '1';
+       when others => null;
+     end case;
+   end process;
+   
+   
+
+
+   -- Instance port mappings.
+   I_dut : ex_19_1_4
+      PORT MAP (
+         A     => A,
+         B     => B,
+         clock => clock,
+         reset => reset,
+         en    => en,
+         dir   => dir
+      );
+
+END struct;

VHD_test/hdl/tb_24_1_5_entity.vhg

@@ -0,0 +1,15 @@
+-- VHDL Entity VHD_test.tb_19_1_5.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:03:49 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
+--
+
+
+ENTITY tb_19_1_5 IS
+-- Declarations
+
+END tb_19_1_5 ;
+

VHD_test/hdl/tb_24_1_5_struct.vhg

@@ -0,0 +1,94 @@
+--
+-- VHDL Architecture VHD_test.tb_19_1_5.struct
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:50:24 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+LIBRARY VHD;
+
+ARCHITECTURE struct OF tb_19_1_5 IS
+
+   -- Architecture declarations
+   constant speedBitNb : positive := 8;
+   
+   constant clockFrequency : real := 100.0E6;
+   constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
+   signal sClock :  std_uLogic := '1';
+   
+   signal position_int : integer := 0;
+
+   -- Internal signal declarations
+   SIGNAL clock : std_ulogic;
+   SIGNAL done  : std_ulogic;
+   SIGNAL reset : std_ulogic;
+   SIGNAL speed : unsigned(speedBitNb-1 DOWNTO 0);
+   SIGNAL start : std_ulogic;
+
+
+   -- Component Declarations
+   COMPONENT ex_19_1_5
+   GENERIC (
+      speedBitNb : positive
+   );
+   PORT (
+      start : IN     std_ulogic ;
+      clock : IN     std_ulogic ;
+      reset : IN     std_ulogic ;
+      done  : OUT    std_ulogic ;
+      speed : OUT    unsigned (speedBitNb-1 DOWNTO 0)
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : ex_19_1_5 USE ENTITY VHD.ex_19_1_5;
+   -- pragma synthesis_on
+
+
+BEGIN
+   -- Architecture concurrent statements
+   -- HDL Embedded Text Block 1 eb1
+   reset <= '1', '0' after 2*clockPeriod;
+   sClock <= not sClock after clockPeriod/2;
+   clock <= transport sClock after clockPeriod*9/10;
+   
+   process
+     constant testDelay: time := 2**(speedBitNb/2+3) * clockPeriod;
+   begin
+     start <= '0';
+   
+     wait for testDelay;
+     start <= '1', '0' after clockPeriod;
+   
+     wait for testDelay;
+     start <= '1', '0' after clockPeriod;
+   
+     wait;
+   end process;
+   
+   
+   
+   
+
+
+   -- Instance port mappings.
+   I_dut : ex_19_1_5
+      GENERIC MAP (
+         speedBitNb => speedBitNb
+      )
+      PORT MAP (
+         start => start,
+         clock => clock,
+         reset => reset,
+         done  => done,
+         speed => speed
+      );
+
+END struct;