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exercice 5

This commit is contained in:
2024-03-22 14:55:12 +01:00
parent 6237811673
commit 8b9202c0ab
4 changed files with 186 additions and 2 deletions

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-- VHDL Entity VHD.ex_24_1_5.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:07:26 03/27/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY ex_24_1_5 IS
GENERIC(
speedBitNb : positive
);
PORT(
start : IN std_ulogic;
clock : IN std_ulogic;
reset : IN std_ulogic;
done : OUT std_ulogic;
speed : OUT unsigned (speedBitNb-1 DOWNTO 0)
);
-- Declarations
END ex_24_1_5 ;

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architecture studentVersion of ex_24_1_5 is
signal running : std_ulogic;
signal deccel : std_ulogic;
signal counter : unsigned(speedBitNb/2-1 downto 0);
signal accumulator : unsigned(speedBitNb-1 downto 0);
begin
speed <= (others => '0');
done <= '0';
process(clock, reset) begin
if reset = '1' then
running <= '0';
deccel <= '0';
counter <= (others => '0');
accumulator <= (others => '0');
speed <= (others => '0');
done <= '0';
elsif rising_edge(clock) then
if start = '1' then
running <= '1';
deccel <= '0';
counter <= (others => '0');
accumulator <= (others => '0'); -- Comment this line if you want 2 accel without overflow (l.38-39)
end if;
if running = '1' then
if deccel = '0' then
counter <= counter + 1;
else
counter <= counter - 1;
end if;
accumulator <= accumulator + counter;
speed <= accumulator;
end if;
--if ((counter = 2**(speedBitNb/2-1)) and (deccel = '0')) then -- For 2 accel without overflow
if ((counter = 2**((speedBitNb/2))-2) and (deccel = '0')) then -- For best fit for only one acceleration
deccel <= '1';
done <= '1';
else
done <= '0';
end if;
if ((deccel = '1') and (counter = 0)) then
running <= '0';
end if;
end if;
end process;
end studentVersion;