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06-07-08-09-SystemOnChip/SystemOnChip_test/hdl/ahbBeamer_tester_test.vhd Normal file
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LIBRARY Common_test;
USE Common_test.testUtils.all;
ARCHITECTURE test OF ahbBeamer_tester IS
-- reset and clock
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
signal clock_int: std_uLogic := '1';
signal reset_int: std_uLogic;
-- test information
signal testSeparator : string(1 to 80) := (others => '-');
signal errorTopSeparator : string(1 to 80) := (others => '#');
signal bottomSeparator : string(1 to 80) := (others => '.');
signal indentation : string(1 to 2) := (others => ' ');
signal noteInformation : string(1 to 9) := (others => ' ');
signal errorInformation : string(1 to 10) := (others => ' ');
signal failureInformation : string(1 to 12) := (others => ' ');
signal testInformation : string(1 to 50) := (others => ' ');
-- register definition
constant controlRegisterAddress: natural := 0;
constant controlRun: natural := 2#001#;
constant controlUpdatePattern: natural := 2#010#;
constant controlInterpolateLinear: natural := 2#100#;
constant speedRegisterAddress: natural := 1;
constant xFifoRegisterAddress: natural := 2;
constant yFifoRegisterAddress: natural := 3;
signal updatePeriod: natural := 1;
signal patternLength: natural := 32;
-- AMBA bus access
constant registerWriteDelay: time := 4*clockPeriod;
signal registerAddress: natural;
signal registerDataOut, registerDataIn: integer;
signal registerWrite: std_uLogic;
signal registerRead: std_uLogic;
-- UART access
constant baudPeriodNb: positive := 4;
signal uartData: integer;
signal uartSend: std_uLogic;
-- functions
function clearBits (word, bits : natural) return natural is
variable andMask: unsigned(hRData'range);
begin
andMask := not(to_unsigned(bits, hRData'length));
return to_integer(to_unsigned(word, hRData'length) and andMask);
end clearBits;
BEGIN
------------------------------------------------------------------------------
-- reset and clock
reset_int <= '1', '0' after 2*clockPeriod;
hReset_n <= not(reset_int);
reset <= reset_int;
clock_int <= not clock_int after clockPeriod/2;
hClk <= transport clock_int after clockPeriod*9.0/10.0;
clock <= transport clock_int after clockPeriod*9.0/10.0;
------------------------------------------------------------------------------
-- test sequence
testSequence: process
begin
selSinCos <= '0';
registerAddress <= 0;
registerDataOut <= 0;
registerWrite <= '0';
registerRead <= '0';
uartSend <= '0';
wait for 100 ns;
print(cr & cr & cr & cr);
----------------------------------------------------------------------------
-- test control register
wait for 1 us - now;
testInformation <= pad("Testing control register", testInformation'length);
wait for 0 ns;
print(testSeparator & cr & testInformation);
-- set control register bits
wait until rising_edge(clock_int);
registerAddress <= controlRegisterAddress;
registerDataOut <= controlRun + controlUpdatePattern + controlInterpolateLinear;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
-- readback control register
wait until rising_edge(clock_int);
registerAddress <= controlRegisterAddress;
registerRead <= '1', '0' after clockPeriod;
wait for 3*clockPeriod;
assert(registerDataIn = controlRun + controlUpdatePattern + controlInterpolateLinear)
report "Control register write / readback error"
severity error;
wait for registerWriteDelay;
-- stop running and pattern update
wait until rising_edge(clock_int);
registerAddress <= controlRegisterAddress;
registerRead <= '1', '0' after clockPeriod;
wait for 3*clockPeriod;
registerDataOut <= clearBits(registerDataIn, controlRun + controlUpdatePattern);
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
----------------------------------------------------------------------------
-- test speed register
wait for 2 us - now;
testInformation <= pad("Testing speed register", testInformation'length);
wait for 0 ns;
print(testSeparator & cr & testInformation);
-- set speed count value
wait until rising_edge(clock_int);
registerAddress <= speedRegisterAddress;
registerDataOut <= updatePeriod;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
-- readback speed count
wait until rising_edge(clock_int);
registerAddress <= speedRegisterAddress;
registerRead <= '1', '0' after clockPeriod;
wait for 3*clockPeriod;
assert(registerDataIn = updatePeriod)
report "Speed register write / readback error"
severity error;
wait for registerWriteDelay;
----------------------------------------------------------------------------
-- write sinewave data points to RAM
wait for 3 us - now;
testInformation <= pad("Writing sinewaves to RAM", testInformation'length);
wait for 0 ns;
print(testSeparator & cr & testInformation);
-- start pattern update
wait until rising_edge(clock_int);
registerAddress <= controlRegisterAddress;
registerDataOut <= controlUpdatePattern;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
-- write X FIFO values
wait until rising_edge(clock_int);
registerAddress <= xFifoRegisterAddress;
registerDataOut <= 16#0000#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#18F9#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#30FB#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#471C#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#5A82#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#6A6D#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#7641#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#7D89#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#7FFF#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#7D89#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#7641#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#6A6D#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#5A82#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#471C#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#30FB#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#18F9#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#0000#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#18F9#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#30FB#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#471C#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#5A82#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#6A6D#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#7641#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#7D89#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#7FFF#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#7D89#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#7641#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#6A6D#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#5A82#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#471C#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#30FB#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#18F9#;
registerWrite <= '1', '0' after clockPeriod;
wait for 10*registerWriteDelay;
-- write Y FIFO values
wait until rising_edge(clock_int);
registerAddress <= yFifoRegisterAddress;
registerDataOut <= 16#7FFF#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#7D89#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#7641#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#6A6D#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#5A82#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#471C#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#30FB#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#18F9#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#0000#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#18F9#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#30FB#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#471C#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#5A82#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#6A6D#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#7641#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#7D89#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#7FFF#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#7D89#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#7641#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#6A6D#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#5A82#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#471C#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#30FB#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#18F9#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#0000#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#18F9#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#30FB#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#471C#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#5A82#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#6A6D#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#7641#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#7D89#;
registerWrite <= '1', '0' after clockPeriod;
wait for 10*registerWriteDelay;
-- end pattern update
wait until rising_edge(clock_int);
registerAddress <= controlRegisterAddress;
registerDataOut <= 0;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
----------------------------------------------------------------------------
-- playing waveforms
wait for 7 us - now;
testInformation <= pad("Playing waveforms", testInformation'length);
wait for 0 ns;
print(testSeparator & cr & testInformation);
-- start run
wait until rising_edge(clock_int);
registerAddress <= controlRegisterAddress;
registerDataOut <= controlRun + patternLength * 2**(hWData'length-patternAddressBitNb);
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
-- run for some time
wait for 250 us - now;
-- stop run
wait until rising_edge(clock_int);
registerAddress <= controlRegisterAddress;
registerDataOut <= 0;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
----------------------------------------------------------------------------
-- play data points to RAM for overflow
wait for 300 us - now;
testInformation <= pad(
"Writing waveform to RAM for overflow", testInformation'length
);
wait for 0 ns;
print(testSeparator & cr & testInformation);
-- start pattern update
wait until rising_edge(clock_int);
registerAddress <= controlRegisterAddress;
registerDataOut <= controlUpdatePattern;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
-- write X FIFO values
wait until rising_edge(clock_int);
registerAddress <= xFifoRegisterAddress;
registerDataOut <= 16#4000#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#7000#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#7000#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#7000#;
registerWrite <= '1', '0' after clockPeriod;
wait for 10*registerWriteDelay;
-- write Y FIFO values
wait until rising_edge(clock_int);
registerAddress <= yFifoRegisterAddress;
registerDataOut <= -16#4000#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#7000#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= 16#7000#;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
registerDataOut <= -16#7000#;
registerWrite <= '1', '0' after clockPeriod;
wait for 10*registerWriteDelay;
-- end pattern update and start run
patternLength <= 4;
wait until rising_edge(clock_int);
registerAddress <= controlRegisterAddress;
registerDataOut <= controlRun + patternLength * 2**(hWData'length-patternAddressBitNb);
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
-- set lower speed execution
updatePeriod <= 9;
wait until rising_edge(clock_int);
registerAddress <= speedRegisterAddress;
registerDataOut <= updatePeriod;
registerWrite <= '1', '0' after clockPeriod;
wait for registerWriteDelay;
----------------------------------------------------------------------------
-- sin/cos debug mode
wait for 700 us - now;
testInformation <= pad("Drawing debug mode circle", testInformation'length);
wait for 0 ns;
print(testSeparator & cr & testInformation);
selSinCos <= '1';
----------------------------------------------------------------------------
-- stop simulation
wait for 1 ms - now;
assert false
report "End" & cr & " --> " &
"End of simulation"
severity failure;
end process testSequence;
------------------------------------------------------------------------------
-- AMBA bus access
busAccess: process
variable writeAccess: boolean;
variable hRData01: std_ulogic_vector(hRData'range);
begin
hAddr <= (others => '-');
hWData <= (others => '-');
hTrans <= transIdle;
hSel <= '0';
hWrite <= '0';
wait on registerWrite, registerRead;
writeAccess := false;
if rising_edge(registerWrite) then
writeAccess := true;
end if;
-- phase 1: address and controls
wait until rising_edge(clock_int);
hAddr <= to_unsigned(registerAddress, hAddr'length);
hTrans <= transNonSeq;
hSel <= '1';
if writeAccess then
hWrite <= '1';
end if;
-- phase 2: data
wait until rising_edge(clock_int);
hAddr <= (others => '-');
hTrans <= transIdle;
hSel <= '0';
hWrite <= '0';
if writeAccess then
hWData <= std_uLogic_vector(to_signed(registerDataOut, hWData'length));
else
wait until falling_edge(clock_int);
hRData01 := hRData;
for index in hRData01'range loop
if (hRData01(index) /= '0') and (hRData01(index) /= '1') then
hRData01(index) := '0';
end if;
end loop;
registerDataIn <= to_integer(unsigned(hRData01));
end if;
wait until rising_edge(clock_int);
end process;
END ARCHITECTURE test;

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06-07-08-09-SystemOnChip/SystemOnChip_test/hdl/beamerSoc_tester_test.vhd Normal file
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ARCHITECTURE test OF beamerSoc_tester IS
-- clock and reset
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
signal sClock: std_uLogic := '1';
signal sReset: std_uLogic := '1';
-- register definition
constant beamerBaseAddress: natural := 16#20#;
constant beamerControlRegisterAddress: natural := beamerBaseAddress + 0;
constant beamerControlRun: natural := 2#001#;
constant beamerControlUpdatePattern: natural := 2#010#;
constant beamerControlInterpolateLinear: natural := 2#100#;
constant beamerControlsizeBase: natural := 16#80#;
constant beamerSpeedRegisterAddress: natural := beamerBaseAddress + 1;
constant beamerXFifoRegisterAddress: natural := beamerBaseAddress + 2;
constant beamerYFifoRegisterAddress: natural := beamerBaseAddress + 3;
-- microprocessor bus access
constant registerWriteDelay: time := 4*clockPeriod;
signal registerAddress: natural;
signal registerDataOut, registerDataIn: integer;
signal registerWrite, registerRead, registerDone: std_uLogic;
-- UART access
-- constant uartFrequency: real := 115200.0;
constant uartDataBitNb: positive := 8;
constant uartFrequency: real := 1.0E6;
constant uartPeriod: time := (1.0/uartFrequency) * 1 sec;
constant uartDataSpan: time := 10*uartPeriod;
constant uartWriteReplySpan: time := 5*uartDataSpan;
constant uartReadReplySpan: time := 10*uartDataSpan;
signal uartRxData, uartTxData: integer;
signal uartSend, uartDone: std_uLogic;
signal uartTxShiftRegister: unsigned(2*uartDataBitNb-1 downto 0);
signal uartTxDataWord: integer;
BEGIN
------------------------------------------------------------------------------
-- clock and reset
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after clockPeriod*9/10;
reset <= '1', '0' after 2*clockPeriod;
------------------------------------------------------------------------------
-- test sequence
process
begin
io <= (others => 'Z');
selSinCos <= '0';
wait for 1 ns;
assert false
report cr & cr & cr & cr &
"----------------------------------------" &
"----------------------------------------" &
"----------------------------------------"
severity note;
----------------------------------------------------------------------------
-- initialization by microprocessor
wait for 100 ns - now;
assert false
report "Init" & cr & " --> " &
"Letting the microprocessor initialize the peripherals"
severity note;
----------------------------------------------------------------------------
-- test GPIOs
wait for 400 ns - now;
assert false
report "GPIOs" & cr & " --> " &
"Testing the GPIOs"
severity note;
io(7 downto 4) <= x"5";
wait for 1 ns;
assert io = x"5A"
report "GPIO error"
severity error;
----------------------------------------------------------------------------
-- set speed count value
wait for 3*uartPeriod - now;
assert false
report "Beamer init" & cr & " --> " &
"Setting drawing speed"
severity note;
registerAddress <= beamerSpeedRegisterAddress;
registerDataOut <= 2;
--registerAddress <= 16#1234#;
--registerDataOut <= 16#5678#;
registerWrite <= '1', '0' after clockPeriod;
wait for uartPeriod;
wait until registerDone = '1';
wait for uartWriteReplySpan;
----------------------------------------------------------------------------
-- start updating pattern
assert false
report "Beamer init" & cr & " --> " &
"Writing y-pattern to beamer RAM"
severity note;
registerAddress <= beamerControlRegisterAddress;
registerDataOut <= beamerControlUpdatePattern;
registerWrite <= '1', '0' after clockPeriod;
wait for uartPeriod;
wait until registerDone = '1';
wait for uartWriteReplySpan;
----------------------------------------------------------------------------
-- write y-FIFO
registerAddress <= beamerYFifoRegisterAddress;
registerDataOut <= -16#4000# + 16#10000#;
registerWrite <= '1', '0' after clockPeriod;
wait for uartPeriod;
wait until registerDone = '1';
wait for uartWriteReplySpan;
registerDataOut <= 16#7000#;
registerWrite <= '1', '0' after clockPeriod;
wait for uartPeriod;
wait until registerDone = '1';
wait for uartWriteReplySpan;
registerDataOut <= 16#7000#;
registerWrite <= '1', '0' after clockPeriod;
wait for uartPeriod;
wait until registerDone = '1';
wait for uartWriteReplySpan;
registerDataOut <= -16#7000# + 16#10000#;
registerWrite <= '1', '0' after clockPeriod;
wait for uartPeriod;
wait until registerDone = '1';
wait for uartWriteReplySpan;
----------------------------------------------------------------------------
-- start run
assert false
report "Beamer play" & cr & " --> " &
"Launching pattern drawing (setting pattern size and run flag)"
severity note;
registerAddress <= beamerControlRegisterAddress;
registerDataOut <= beamerControlRun + beamerControlsizeBase * 4;
registerWrite <= '1', '0' after clockPeriod;
wait for uartPeriod;
wait until registerDone = '1';
wait for uartWriteReplySpan;
----------------------------------------------------------------------------
-- readback control register
assert false
report "Beamer test" & cr & " --> " &
"Reading back control register"
severity note;
registerAddress <= beamerControlRegisterAddress;
registerRead <= '1', '0' after clockPeriod;
wait for uartPeriod;
wait until registerDone = '1';
wait for uartReadReplySpan;
assert uartTxDataWord = beamerControlRun + beamerControlsizeBase * 4
report "Beamer register readback error"
severity error;
----------------------------------------------------------------------------
-- stop simulation
wait for 1.5 ms - now;
assert false
report "End" & cr & " --> " &
"End of simulation"
severity failure;
end process;
--============================================================================
-- microprocessor bus access
busAccess: process
variable writeAccess: boolean;
-- variable packetId: natural := 0;
variable packetId: natural := 16#1D#;
variable checksum: natural;
begin
registerDone <= '1';
uartSend <= '0';
uartRxData <= 16#AA#;
wait on registerWrite, registerRead;
registerDone <= '0';
writeAccess := false;
if registerWrite = '1' then
writeAccess := true;
end if;
-- send header
uartSend <= '1', '0' after uartPeriod;
wait for uartPeriod;
wait until uartDone = '1';
checksum := uartRxData;
-- send packet id
uartRxData <= packetId;
packetId := (packetId + 1) mod 2**8;
uartSend <= '1', '0' after uartPeriod;
wait for uartPeriod;
wait until uartDone = '1';
checksum := (checksum + uartRxData) mod 2**8;
-- send command
if writeAccess then
uartRxData <= 16#03#;
else
uartRxData <= 16#04#;
end if;
uartSend <= '1', '0' after uartPeriod;
wait for uartPeriod;
wait until uartDone = '1';
checksum := (checksum + uartRxData) mod 2**8;
-- send data length
if writeAccess then
uartRxData <= 4;
else
uartRxData <= 2;
end if;
uartSend <= '1', '0' after uartPeriod;
wait for uartPeriod;
wait until uartDone = '1';
checksum := (checksum + uartRxData) mod 2**8;
-- send addresss low
uartRxData <= registerAddress mod 2**8;
uartSend <= '1', '0' after uartPeriod;
wait for uartPeriod;
wait until uartDone = '1';
checksum := (checksum + uartRxData) mod 2**8;
-- send addresss high
uartRxData <= registerAddress / 2**8;
uartSend <= '1', '0' after uartPeriod;
wait for uartPeriod;
wait until uartDone = '1';
checksum := (checksum + uartRxData) mod 2**8;
-- send data low
if writeAccess then
uartRxData <= registerDataOut mod 2**8;
uartSend <= '1', '0' after uartPeriod;
wait for uartPeriod;
wait until uartDone = '1';
checksum := (checksum + uartRxData) mod 2**8;
-- send data high
uartRxData <= registerDataOut / 2**8;
uartSend <= '1', '0' after uartPeriod;
wait for uartPeriod;
wait until uartDone = '1';
checksum := (checksum + uartRxData) mod 2**8;
end if;
-- send checksum
uartRxData <= checksum;
uartSend <= '1', '0' after uartPeriod;
wait for uartPeriod;
wait until uartDone = '1';
end process;
------------------------------------------------------------------------------
-- UART access
sendByte: process
variable serialData: unsigned(7 downto 0);
begin
-- send stop bit
uartDone <= '1';
RxD <= '1';
-- get new word
wait until rising_edge(uartSend);
uartDone <= '0';
serialData := to_unsigned(uartRxData, serialData'length);
-- send start bit
RxD <= '0';
wait for uartPeriod;
-- send data bits
for index in serialData'reverse_range loop
RxD <= serialData(index);
wait for uartPeriod;
end loop;
-- send stop bits
RxD <= '1';
wait for 4*uartPeriod;
end process sendByte;
------------------------------------------------------------------------------
-- UART access
receiveByte: process
variable serialData: unsigned(uartDataBitNb-1 downto 0);
begin
-- wait for stat bit
wait until falling_edge(TxD);
-- jump to middle of first data bit
wait for 1.5 * uartPeriod;
-- read data bits
for index in serialData'reverse_range loop
if Is_X(TxD) then
serialData(index) := '0';
else
serialData(index) := TxD;
end if;
wait for uartPeriod;
end loop;
-- write data to signal
uartTxData <= to_integer(serialData);
uartTxDataWord <= to_integer(uartTxShiftRegister);
uartTxShiftRegister <= shift_right(uartTxShiftRegister, serialData'length);
uartTxShiftRegister(
uartTxShiftRegister'high downto
uartTxShiftRegister'high-serialData'length+1
) <= serialData;
end process receiveByte;
END ARCHITECTURE test;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
PACKAGE beamerTest_pck IS
function trim_X (arg : signed) return signed;
END beamerTest_pck;

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PACKAGE BODY beamerTest_pck IS
function trim_X (arg : signed) return signed is
variable returnVal : signed(arg'range);
begin
for i in arg'range loop
case arg(i) is
when '0' | 'L' => returnVal(i) := '0';
when '1' | 'H' => returnVal(i) := '1';
when others => returnVal(i) := '0';
end case;
end loop;
return returnVal;
end trim_X;
END beamerTest_pck;

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DIALECT atom VHDL_2008

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1
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DIALECT atom VHDL_2008

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1
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DIALECT atom VHDL_93

1
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DIALECT atom VHDL_2008

1
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DIALECT atom VHDL_2008

1
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DIALECT atom VHDL_2008

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DEFAULT_FILE atom ahb@beamer_tb/struct.bd
DEFAULT_ARCHITECTURE atom struct
TOP_MARKER atom 1

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DEFAULT_ARCHITECTURE atom test
DEFAULT_FILE atom ahbBeamer_tester_test.vhd

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DEFAULT_ARCHITECTURE atom struct
DEFAULT_FILE atom beamer@periph@blanking_tb/struct.bd

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DEFAULT_FILE atom beamer@soc_tb/struct.bd
DEFAULT_ARCHITECTURE atom struct
TOP_MARKER atom 1

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DEFAULT_FILE atom beamerSoc_tester_test.vhd
DEFAULT_ARCHITECTURE atom test

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xt "22600,16000,25900,17200"
st "<cell>"
blo "22600,17000"
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)
gi *21 (GenericInterface
ps "CenterOffsetStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
font "Courier New,8,0"
)
xt "0,12000,0,12000"
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header "Generic Declarations"
)
elements [
]
)
portInstanceVisAsIs 1
portInstanceVis (PortSigDisplay
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)
defaultCptPort (CptPort
ps "OnEdgeStrategy"
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ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
n "In0"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 0
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tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
font "Verdana,9,0"
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xt "0,750,1800,1950"
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blo "0,1750"
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)
dt (MLText
va (VaSet
font "Courier New,8,0"
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)
defaultCptPortBuffer (CptPort
ps "OnEdgeStrategy"
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vasetType 1
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xt "0,0,750,750"
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ps "CptPortTextPlaceStrategy"
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dt (MLText
va (VaSet
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uid 1,0
stg "SymDeclLayoutStrategy"
declLabel (Text
uid 2,0
va (VaSet
font "Arial,8,1"
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xt "42000,0,47400,1000"
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portLabel (Text
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va (VaSet
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xt "42000,1000,44300,2000"
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va (VaSet
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xt "42000,5200,44000,6200"
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va (VaSet
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xt "42000,0,47800,1000"
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externalText (MLText
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va (VaSet
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