Initial commit

Libs/RiscV/HEIRV32/SingleCycle/hdl/dataMemory_rtl.vhd

@@ -0,0 +1,32 @@
+
+ARCHITECTURE rtl OF dataMemory IS
+
+  -- Bank of data
+  type t_dataBank is array (0 to (2**g_memoryNbBits)-1) of
+    std_ulogic_vector(g_dataWidth-1 downto 0);
+  -- A bank of data
+  signal larr_data: t_dataBank;
+
+BEGIN
+
+  process(rst, clk)
+  begin
+    if rst = '1' then
+      larr_data <= (others => (others => '0')) after g_tMemWr;
+    elsif rising_edge(clk) then
+      if en = '1' and writeEn = '1' then
+        -- skip the two last bits (since we do only +4)
+        larr_data(to_integer(unsigned(
+          address(g_memoryNbBits+1 downto 2)
+        ))) <= writeData after (g_tMemWr + g_tSetup);
+      end if;
+    end if;
+  end process;
+
+  -- Comb. read
+    -- skip the two last bits (since we do only +4)
+  readData <= larr_data(to_integer(unsigned(
+    address(g_memoryNbBits+1 downto 2)
+  ))) after g_tMemRd;
+
+END ARCHITECTURE rtl;

Libs/RiscV/HEIRV32/SingleCycle/hdl/instrMemory_bin.vhd

@@ -0,0 +1,34 @@
+USE std.textio.all;
+
+ARCHITECTURE bin OF instrMemory IS
+
+  -- Instructions type
+  type t_instrBank is array (g_memoryNbBits-1 downto 0) of
+    std_ulogic_vector(g_dataWidth-1 downto 0);
+
+  -- Define function to create initvalue signal
+  impure function ReadRamContentFromFile(ramContentFilenAme : in string) return t_instrBank is
+    FILE     ramContentFile     : text is in ramContentFilenAme;
+    variable ramContentFileLine : line;
+    variable ramContent         : t_instrBank;
+  begin
+    for i in t_instrBank'range loop
+      readline(ramContentFile, ramContentFileLine);
+      read(ramContentFileLine, ramContent(i));
+    end loop;
+    return ramContent;
+  end function;
+
+  -- Program
+  constant larr_instr : t_instrBank := ReadRamContentFromFile(g_programFile);
+
+BEGIN
+
+  -- Comb. read
+  process(PC)
+  begin
+    -- skip the two last bits (since we do only +4)
+    instruction <= larr_instr(to_integer(PC(g_memoryNbBits+1 downto 2)));
+  end process;
+  
+END ARCHITECTURE bin;

Libs/RiscV/HEIRV32/SingleCycle/hdl/instrMemory_hex.vhd

@@ -0,0 +1,36 @@
+library ieee;
+  use std.textio.all;
+  use ieee.std_logic_textio.all;
+
+ARCHITECTURE hex OF instrMemory IS
+
+  -- Instructions type
+  type t_instrBank is array (0 to (2**g_memoryNbBits)-1) of
+    std_ulogic_vector(g_dataWidth-1 downto 0);
+
+  -- Define function to create initvalue signal
+  impure function ReadRamContentFromFile(ramContentFilenAme : in string) return t_instrBank is
+    FILE     ramContentFile     : text is in ramContentFilenAme;
+    variable ramContentFileLine : line;
+    variable ramContent         : t_instrBank;
+  begin
+    for i in t_instrBank'range loop
+      readline(ramContentFile, ramContentFileLine);
+      HREAD(ramContentFileLine, ramContent(i));
+    end loop;
+    return ramContent;
+  end function;
+
+  -- Program
+  constant larr_instr : t_instrBank := ReadRamContentFromFile(g_programFile);
+
+BEGIN
+
+  -- Comb. read
+  process(PC)
+  begin
+    -- skip the two last bits (since we do only +4)
+    instruction <= larr_instr(to_integer(PC(g_memoryNbBits+1 downto 2))) after g_tMemRd;
+  end process;
+  
+END ARCHITECTURE hex;

Libs/RiscV/HEIRV32/SingleCycle/hdl/mainDecoder_rtl.vhd

@@ -0,0 +1,24 @@
+
+ARCHITECTURE rtl OF mainDecoder IS
+
+  signal lvec_controls : std_ulogic_vector(10 downto 0);
+
+BEGIN
+
+  process(op)
+  begin
+    case op is
+      when "0000011" => lvec_controls <= "10010010000"; -- lw
+      when "0100011" => lvec_controls <= "00111000000"; -- sw
+      when "0110011" => lvec_controls <= "1--00000100"; -- R-type
+      when "1100011" => lvec_controls <= "01000001010"; -- beq
+      when "0010011" => lvec_controls <= "10010000100"; -- I-type ALU
+      when "1101111" => lvec_controls <= "11100100001"; -- jal
+      when others    => lvec_controls <= "-----------"; -- not valid
+    end case;
+  end process;
+
+  (regwrite, immSrc(1), immSrc(0), ALUSrc, memWrite, resultSrc(1), resultSrc(0),
+    branch, ALUOp(1), ALUOp(0), jump) <= lvec_controls after g_tDec;
+
+END ARCHITECTURE rtl;

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_controlunit_masterversion.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_dataMemory_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_bin.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_hex.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_mainDecoder_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_rtl_instrMemory.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/_bin._epf

@@ -0,0 +1,2 @@
+DEFAULT_FILE atom rtl_instrMemory.vhd
+DEFAULT_ARCHITECTURE atom instrMemory

Libs/RiscV/HEIRV32/SingleCycle/hds/_controlunit._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom masterVersion
+DEFAULT_FILE atom control@unit/master@version.bd

Libs/RiscV/HEIRV32/SingleCycle/hds/_datamemory._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom dataMemory_rtl.vhd

Libs/RiscV/HEIRV32/SingleCycle/hds/_heirv32_sc._epf

@@ -0,0 +1,3 @@
+TOP_MARKER atom 1
+DEFAULT_FILE atom heirv32_sc/struct.bd
+DEFAULT_ARCHITECTURE atom struct

Libs/RiscV/HEIRV32/SingleCycle/hds/_instrmemory._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom hex
+DEFAULT_FILE atom instrMemory_hex.vhd

Libs/RiscV/HEIRV32/SingleCycle/hds/_maindecoder._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom mainDecoder_rtl.vhd