Initial commit

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_controlunit_masterversion.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_dataMemory_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_bin.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_hex.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_mainDecoder_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_rtl_instrMemory.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/_bin._epf

@@ -0,0 +1,2 @@
+DEFAULT_FILE atom rtl_instrMemory.vhd
+DEFAULT_ARCHITECTURE atom instrMemory

Libs/RiscV/HEIRV32/SingleCycle/hds/_controlunit._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom masterVersion
+DEFAULT_FILE atom control@unit/master@version.bd

Libs/RiscV/HEIRV32/SingleCycle/hds/_datamemory._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom dataMemory_rtl.vhd

Libs/RiscV/HEIRV32/SingleCycle/hds/_heirv32_sc._epf

@@ -0,0 +1,3 @@
+TOP_MARKER atom 1
+DEFAULT_FILE atom heirv32_sc/struct.bd
+DEFAULT_ARCHITECTURE atom struct

Libs/RiscV/HEIRV32/SingleCycle/hds/_instrmemory._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom hex
+DEFAULT_FILE atom instrMemory_hex.vhd

Libs/RiscV/HEIRV32/SingleCycle/hds/_maindecoder._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom mainDecoder_rtl.vhd