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fix coeff calculation

This commit is contained in:
2024-03-10 21:50:07 +01:00
parent cf05b0a7f9
commit e187e34017
8 changed files with 37 additions and 16 deletions

View File

@ -1,4 +1,20 @@
ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS
subtype sample_type is signed(sampleIn'range);
type samples_type is array (1 to 4) of sample_type;
signal samples: samples_type;
BEGIN
process(clock, reset) begin
if reset = '1' then
samples <= (others => (others => '0'));
elsif rising_edge(clock) then
end if;
end process;
sampleOut <= (others => '0');
END ARCHITECTURE studentVersion;

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@ -10,18 +10,18 @@ BEGIN
-- a = - sample1 +3·sample2 -3·sample3 + sample4
-- b = 2·sample1 -5·sample2 +4·sample3 - sample4
-- c = - sample1 + sample3
-- d = sample2
-- d = sample2
process(sample1, sample2, sample3, sample4) begin
samples(4) <= resize(sample1, coeff'high+1);
samples(3) <= resize(sample2, coeff'high+1);
samples(2) <= resize(sample3, coeff'high+1);
samples(1) <= resize(sample4, coeff'high+1);
samples(1) <= resize(sample1, coeff'high+1);
samples(2) <= resize(sample2, coeff'high+1);
samples(3) <= resize(sample3, coeff'high+1);
samples(4) <= resize(sample4, coeff'high+1);
end process;
a <= samples(4) - samples(1) + resize( 3*(samples(2) - samples(3)), coeff'high+1);
b <= resize(2*samples(1), coeff'high+1) - resize(5*samples(2), coeff'high+1) + resize(4*samples(3), coeff'high+1) - samples(4);
c <= samples(3) - samples(1);
d <= samples(4);
d <= samples(2);
END ARCHITECTURE studentVersion;

View File

@ -10,17 +10,19 @@ BEGIN
if reset = '1' then
samples <= (others => (others => '0'));
elsif rising_edge(clock) then
if shiftSamples then
for i in samples_type'low to samples_type'high-1 loop
samples(i+1) <= samples(i);
end loop;
samples(1) <= sampleIn;
end if;
end if;
end process;
sample1 <= samples(1);
sample2 <= samples(2);
sample3 <= samples(3);
sample4 <= samples(4);
sample1 <= samples(4);
sample2 <= samples(3);
sample3 <= samples(2);
sample4 <= samples(1);
END ARCHITECTURE studentVersion;

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@ -7,11 +7,13 @@ BEGIN
process(clock, reset)
begin
if reset = '1' then
counter <= (others => '1');
counter <= (others => '0');
elsif rising_edge(clock) then
if en = '1' then
counter <= counter - 1;
end if;
end if;
end process;
@ -23,5 +25,5 @@ BEGIN
triggerOut <= '0';
end if;
end process;
END ARCHITECTURE studentVersion;