Klagarge/SRE
1
0
Fork 0
Code Issues Pull Requests Actions Releases Activity

ADD week 4

Browse Source
This commit is contained in:
Rémi Heredero
2025-03-31 16:31:52 +02:00
parent 84135a321e
commit 86f265f22d
119 changed files with 2243 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
03-Average1/A1-vscode/data/README.txt Executable file
View File

@ -0,0 +1,15 @@
The "data" directory is intended to hold data files that will be used by this module and will
not end up in the .jar file, but will be present in the zip or tar file. Typically, data
files are placed here rather than in the resources directory if the user may need to edit them.
An optional data/languages directory can exist for the purpose of containing various Sleigh language
specification files and importer opinion files.
The data/buildLanguage.xml is used for building the contents of the data/languages directory.
The skel language definition has been commented-out within the skel.ldefs file so that the
skeleton language does not show-up within Ghidra.
See the Sleigh language documentation (docs/languages/index.html) for details Sleigh language
specification syntax.

50
03-Average1/A1-vscode/data/buildLanguage.xml Executable file
View File

@ -0,0 +1,50 @@
<?xml version="1.0" encoding="UTF-8"?>
<!--
+ Compile sleigh languages within this module.
+ Sleigh compiler options are read from the sleighArgs.txt file.
+ Eclipse: right-click on this file and choose menu item "Run As->Ant Build"
-->
<project name="privateBuildDeveloper" default="sleighCompile">
<property name="sleigh.compile.class" value="ghidra.pcodeCPort.slgh_compile.SleighCompile"/>
<!--Import optional ant properties. GhidraDev Eclipse plugin produces this so this file can find the Ghidra installation-->
<import file="../.antProperties.xml" optional="false" />
<target name="sleighCompile">
<!-- If language module is detached from installation, get Ghidra installation directory path from imported properties -->
<property name="framework.path" value="${ghidra.install.dir}/Ghidra/Framework"/>
<path id="sleigh.class.path">
<fileset dir="${framework.path}/SoftwareModeling/lib">
<include name="*.jar"/>
</fileset>
<fileset dir="${framework.path}/Generic/lib">
<include name="*.jar"/>
</fileset>
<fileset dir="${framework.path}/Utility/lib">
<include name="*.jar"/>
</fileset>
</path>
<available classname="${sleigh.compile.class}" classpathref="sleigh.class.path" property="sleigh.compile.exists"/>
<fail unless="sleigh.compile.exists" />
<java classname="${sleigh.compile.class}"
classpathref="sleigh.class.path"
fork="true"
failonerror="true">
<jvmarg value="-Xmx2048M"/>
<arg value="-i"/>
<arg value="sleighArgs.txt"/>
<arg value="-a"/>
<arg value="./languages"/>
</java>
</target>
</project>

121
03-Average1/A1-vscode/data/languages/skel.cspec Executable file
View File

@ -0,0 +1,121 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/compiler_spec.rxg -->
<compiler_spec>
<data_organization>
<pointer_size value="2" />
</data_organization>
<global>
<range space="ram"/>
<range space="io"/>
</global>
<stackpointer register="SP" space="ram"/>
<default_proto>
<prototype name="__asmA" extrapop="2" stackshift="2" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="BC"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="HL"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="DE"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IY"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="2" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="BC_"/>
<register name="HL_"/>
<register name="DE_"/>
<register name="AF_"/>
<register name="rBBR"/>
</unaffected>
</prototype>
</default_proto>
<prototype name="__asmAF" extrapop="2" stackshift="2" strategy="register">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="BC"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="HL"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="DE"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IY"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="IX"/>
</pentry>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="2" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="2">
<register name="AF"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="rBBR"/>
<register name="BC_"/>
<register name="HL_"/>
<register name="DE_"/>
<register name="AF_"/>
</unaffected>
</prototype>
<prototype name="__stdcall" extrapop="2" stackshift="2">
<input>
<pentry minsize="1" maxsize="1">
<register name="A"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="BC"/>
</pentry>
<pentry minsize="1" maxsize="2">
<register name="HL"/>
</pentry>
<pentry minsize="1" maxsize="500" align="2">
<addr offset="2" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="1">
<register name="AF"/>
</pentry>
</output>
<unaffected>
<register name="SP"/>
<register name="rBBR"/>
<register name="BC_"/>
<register name="HL_"/>
<register name="DE_"/>
<register name="AF_"/>
</unaffected>
</prototype>
</compiler_spec>

20
03-Average1/A1-vscode/data/languages/skel.ldefs Executable file
View File

@ -0,0 +1,20 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/language_definitions.rxg -->
<language_definitions>
<!-- Uncomment the following to make the language available in Ghidra -->
<!--
<language processor="Skel"
endian="little"
size="16"
variant="default"
version="1.0"
slafile="skel.sla"
processorspec="skel.pspec"
id="skel:LE:16:default">
<description>Skeleton Language Module</description>
<compiler name="default" spec="skel.cspec" id="default"/>
</language>
-->
</language_definitions>

12
03-Average1/A1-vscode/data/languages/skel.opinion Executable file
View File

@ -0,0 +1,12 @@
<opinions>
<!-- Example of importer opinions - commented-out to prevent use by Ghidra -->
<!-- The primary and secondary constraint values must be specifide as a decimal string -->
<!--
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
<constraint primary="40" secondary="123" processor="Skel" size="16" variant="default" />
</constraint>
<constraint loader="MS Common Object File Format (COFF)" compilerSpecID="default">
<constraint primary="61" processor="Skel" size="16" variant="default" />
</constraint>
-->
</opinions>

23
03-Average1/A1-vscode/data/languages/skel.pspec Executable file
View File

@ -0,0 +1,23 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- See Relax specification: Ghidra/Framework/SoftwareModeling/data/languages/processor_spec.rxg -->
<processor_spec>
<programcounter register="PC"/>
<register_data>
<register name="AF_" group="Alt"/>
<register name="BC_" group="Alt"/>
<register name="DE_" group="Alt"/>
<register name="HL_" group="Alt"/>
</register_data>
<default_symbols>
<symbol name="RST0" address="ram:0000" entry="true"/>
<symbol name="RST1" address="ram:0008" entry="false"/>
<symbol name="RST2" address="ram:0010" entry="false"/>
<symbol name="RST3" address="ram:0018" entry="false"/>
<symbol name="RST4" address="ram:0020" entry="false"/>
<symbol name="RST5" address="ram:0028" entry="false"/>
<symbol name="RST6" address="ram:0030" entry="false"/>
<symbol name="RST7" address="ram:0038" entry="false"/>
</default_symbols>
</processor_spec>

220
03-Average1/A1-vscode/data/languages/skel.sinc Executable file
View File

@ -0,0 +1,220 @@
# sleigh include file for Skeleton language instructions
define token opbyte (8)
op0_8 = (0,7)
op6_2 = (6,7)
dRegPair4_2 = (4,5)
pRegPair4_2 = (4,5)
sRegPair4_2 = (4,5)
qRegPair4_2 = (4,5)
qRegPair4_2a = (4,5)
qRegPair4_2b = (4,5)
rRegPair4_2 = (4,5)
reg3_3 = (3,5)
bits3_3 = (3,5)
bits0_4 = (0,3)
reg0_3 = (0,2)
bits0_3 = (0,2)
;
define token data8 (8)
imm8 = (0,7)
sign8 = (7,7)
simm8 = (0,7) signed
;
define token data16 (16)
timm4 = (12,15)
imm16 = (0,15)
sign16 = (15,15)
simm16 = (0,15) signed
;
attach variables [ reg0_3 reg3_3 ] [ B C D E H L _ A ];
attach variables [ sRegPair4_2 dRegPair4_2 ] [ BC DE HL SP ];
attach variables [ qRegPair4_2 ] [ BC DE HL AF ];
attach variables [ qRegPair4_2a ] [ B D H A ];
attach variables [ qRegPair4_2b ] [ C E L F ];
attach variables [ pRegPair4_2 ] [ BC DE IX SP ];
attach variables [ rRegPair4_2 ] [ BC DE IY SP ];
################################################################
# Macros
################################################################
macro setResultFlags(result) {
$(Z_flag) = (result == 0);
$(S_flag) = (result s< 0);
}
macro setAddCarryFlags(op1,op2) {
$(C_flag) = (carry(op1,zext($(C_flag))) || carry(op2,op1 + zext($(C_flag))));
}
macro setAddFlags(op1,op2) {
$(C_flag) = carry(op1,op2);
}
macro setSubtractCarryFlags(op1,op2) {
notC = ~$(C_flag);
$(C_flag) = ((op1 < sext(notC)) || (op2 < (op1 - sext(notC))));
}
macro setSubtractFlags(op1,op2) {
$(C_flag) = (op1 < op2);
}
macro push16(val16) {
SP = SP - 2;
*:2 SP = val16;
}
macro pop16(ret16) {
ret16 = *:2 SP;
SP = SP + 2;
}
macro push8(val8) {
SP = SP - 1;
ptr:2 = SP;
*:1 ptr = val8;
}
macro pop8(ret8) {
ptr:2 = SP;
ret8 = *:1 ptr;
SP = SP + 1;
}
################################################################
ixMem8: (IX+simm8) is IX & simm8 { ptr:2 = IX + simm8; export *:1 ptr; }
ixMem8: (IX-val) is IX & simm8 & sign8=1 [ val = -simm8; ] { ptr:2 = IX + simm8; export *:1 ptr; }
iyMem8: (IY+simm8) is IY & simm8 { ptr:2 = IY + simm8; export *:1 ptr; }
iyMem8: (IY-val) is IY & simm8 & sign8=1 [ val = -simm8; ] { ptr:2 = IY + simm8; export *:1 ptr; }
Addr16: imm16 is imm16 { export *:1 imm16; }
Mem16: (imm16) is imm16 { export *:2 imm16; }
RelAddr8: loc is simm8 [ loc = inst_next + simm8; ] { export *:1 loc; }
cc: "NZ" is bits3_3=0x0 { c:1 = ($(Z_flag) == 0); export c; }
cc: "Z" is bits3_3=0x1 { c:1 = $(Z_flag); export c; }
cc: "NC" is bits3_3=0x2 { c:1 = ($(C_flag) == 0); export c; }
cc: "C" is bits3_3=0x3 { c:1 = $(C_flag); export c; }
cc: "PO" is bits3_3=0x4 { c:1 = ($(PV_flag) == 0); export c; }
cc: "PE" is bits3_3=0x5 { c:1 = $(PV_flag); export c; }
cc: "P" is bits3_3=0x6 { c:1 = ($(S_flag) == 0); export c; }
cc: "M" is bits3_3=0x7 { c:1 = $(S_flag); export c; }
cc2: "NZ" is bits3_3=0x4 { c:1 = ($(Z_flag) == 0); export c; }
cc2: "Z" is bits3_3=0x5 { c:1 = $(Z_flag); export c; }
cc2: "NC" is bits3_3=0x6 { c:1 = ($(C_flag) == 0); export c; }
cc2: "C" is bits3_3=0x7 { c:1 = $(C_flag); export c; }
################################################################
:LD IX,Mem16 is op0_8=0xdd & IX; op0_8=0x2a; Mem16 {
IX = Mem16;
}
:LD IY,Mem16 is op0_8=0xfd & IY; op0_8=0x2a; Mem16 {
IY = Mem16;
}
:LD Mem16,HL is op0_8=0x22 & HL; Mem16 {
Mem16 = HL;
}
:LD Mem16,dRegPair4_2 is op0_8=0xed; op6_2=0x1 & dRegPair4_2 & bits0_4=0x3; Mem16 {
Mem16 = dRegPair4_2;
}
:LD Mem16,IX is op0_8=0xdd & IX; op0_8=0x22; Mem16 {
Mem16 = IX;
}
:LD Mem16,IY is op0_8=0xfd & IY; op0_8=0x22; Mem16 {
Mem16 = IY;
}
:NEG is op0_8=0xed; op0_8=0x44 {
$(PV_flag) = (A == 0x80);
$(C_flag) = (A != 0);
A = -A;
setResultFlags(A);
}
:SET bits3_3,ixMem8 is op0_8=0xdd; op0_8=0xcb; ixMem8; op6_2=0x3 & bits3_3 & bits0_3=0x6 {
mask:1 = (1 << bits3_3);
val:1 = ixMem8;
ixMem8 = val | mask;
}
:SET bits3_3,iyMem8 is op0_8=0xfd; op0_8=0xcb; iyMem8; op6_2=0x3 & bits3_3 & bits0_3=0x6 {
mask:1 = (1 << bits3_3);
val:1 = iyMem8;
iyMem8 = val | mask;
}
:JP Addr16 is op0_8=0xc3; Addr16 {
goto Addr16;
}
:JP cc,Addr16 is op6_2=0x3 & cc & bits0_3=0x2; Addr16 {
if (!cc) goto Addr16;
}
:JR RelAddr8 is op0_8=0x18; RelAddr8 {
goto RelAddr8;
}
:JR cc2,RelAddr8 is op6_2=0x0 & cc2 & bits0_3=0x0; RelAddr8 {
if (cc2) goto RelAddr8;
}
:JP (HL) is op0_8=0xe9 & HL {
goto [HL];
}
:JP (IX) is op0_8=0xdd & IX; op0_8=0xe9 {
goto [IX];
}
:JP (IY) is op0_8=0xfd & IY; op0_8=0xe9 {
goto [IY];
}
:CALL Addr16 is op0_8=0xcd; Addr16 {
push16(&:2 inst_next);
call Addr16;
}
:CALL cc,Addr16 is op6_2=0x3 & cc & bits0_3=0x4; Addr16 {
if (!cc) goto inst_next;
push16(&:2 inst_next);
call Addr16;
}
:RET is op0_8=0xc9 {
pop16(PC);
ptr:2 = zext(PC);
return [ptr];
}
:RET cc is op6_2=0x3 & cc & bits0_3=0x0 {
if (!cc) goto inst_next;
pop16(PC);
ptr:2 = zext(PC);
return [ptr];
}

39
03-Average1/A1-vscode/data/languages/skel.slaspec Executable file
View File

@ -0,0 +1,39 @@
# sleigh specification file for Skeleton Processor
# >> see docs/languages/sleigh.htm or sleigh.pdf for Sleigh syntax
# Other language modules (see Ghidra/Processors) may provide better examples
# when creating a new language module.
define endian=little;
define alignment=1;
define space ram type=ram_space size=2 default;
define space io type=ram_space size=2;
define space register type=register_space size=1;
define register offset=0x00 size=1 [ F A C B E D L H I R ];
define register offset=0x00 size=2 [ AF BC DE HL ];
define register offset=0x20 size=1 [ A_ F_ B_ C_ D_ E_ H_ L_ ]; # Alternate registers
define register offset=0x20 size=2 [ AF_ BC_ DE_ HL_ ]; # Alternate registers
define register offset=0x40 size=2 [ _ PC SP IX IY ];
define register offset=0x50 size=1 [ rCBAR rCBR rBBR ];
# Define context bits (if defined, size must be multiple of 4-bytes)
define register offset=0xf0 size=4 contextreg;
define context contextreg
assume8bitIOSpace = (0,0)
;
# Flag bits (?? manual is very confusing - could be typos!)
@define C_flag "F[0,1]" # C: Carry
@define N_flag "F[1,1]" # N: Add/Subtract
@define PV_flag "F[2,1]" # PV: Parity/Overflow
@define H_flag "F[4,1]" # H: Half Carry
@define Z_flag "F[6,1]" # Z: Zero
@define S_flag "F[7,1]" # S: Sign
# Include contents of skel.sinc file
@include "skel.sinc"

6
03-Average1/A1-vscode/data/sleighArgs.txt Executable file
View File

@ -0,0 +1,6 @@
# Add sleigh compiler options to this file (one per line) which will
# be used when compiling each language within this module.
# All options should start with a '-' character.
#
# IMPORTANT: The -a option should NOT be specified
#