David Stadelmann d9abaf4a53 feat: add pentagon-shaped ports
Add an optional pentagon shape for block and group ports, configured via
the element-level `port-shape`, `port-kind` and `port-size` parameters.
Individual ports can override them with `shape`, `kind`, `size`,
`stroke` and `fill`. Clock ports with a pentagon shape drop the clock
triangle and default to a gray fill.

Wires attach to the outer end of the pentagon by default. With the new
`shell` parameter on `element.elmt` they attach to the inner tip
instead.

Each port is exposed as a CeTZ group with a `default` anchor plus the
cardinal sub-anchors `.east`, `.west`, `.north` and `.south` on the
pentagon's bounding box, so wires can attach to any face. For
non-pentagon ports the sub-anchors collapse to the default attach point,
and the bare `<elmt-id>-port-<port-id>` anchor resolves as before.

Add the `port-shape` and `port-shape-attach` examples and the
`gallery/test_port_shape` gallery entry.
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circuiteria

Circuiteria is a Typst package for drawing block circuit diagrams using the CeTZ package.

A platypus / Perry the Platypus meme made with colored rounded rectangles

Examples

Block diagram of a multi-cycle RISC-V FPGA processor
A bit of everything
Block diagram of a single-cycle RISC-V processor
Wires everywhere
Top-level block diagram of a single-cycle RISC-V processor Block diagram of a simple single-cycle RISC-V ALU
Groups Rotated

Note


These circuit layouts were copied from a digital design course given by prof. S. Zahno and recreated using this package

Click on the example image to jump to the code.

Usage

For more information, see the manual

To use this package, simply import circuiteria and call the circuit function:

#import "@preview/circuiteria:0.2.1"
#circuiteria.circuit({
  import circuiteria: *
  ...
})
S
Description
Drawing block circuits with Typst made easy, using CeTZ
Readme Apache-2.0
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