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Add Verilog parsing and rendering support #26

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purpl3F0x wants to merge 5 commits from purpl3F0x/circuiteria:main into main
pull from: purpl3F0x/circuiteria:main
merge into: HEL:main
Conversation 1 Commits 5 Files Changed 11
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5 Commits
Author SHA1 Message Date
purpl3F0xandClaude Opus 5.5 6b861553b7 Pack and center Verilog block ports with automatic spacing 
- Add `ports-align` ("center" by default, "top", "bottom", or "spread" for
  the previous evenly spread layout) and `ports-pitch` to `verilog.block`.
- Packed layouts use minimal margins, only reserving room for the module
  name and north/south ports, and size the block to the busiest side.
- The automatic height now also adapts to custom `ports-margins`.
- Regenerate the gallery image and the manual.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Signed-off-by: Stavros Avramidis <stavros9899@gmail.com>
 2026-11-03 13:31:07 +02:00
purpl3F0x 7c3eb26aa3 Enhance Verilog support by adding BRAM read/write port handling and updating documentation 
Signed-off-by: Stavros Avramidis <stavros9899@gmail.com>
 2026-11-03 13:18:43 +02:00
purpl3F0x 58f821070a Add APB support 
Signed-off-by: Stavros Avramidis <stavros9899@gmail.com>
 2026-11-03 13:03:22 +02:00
purpl3F0x e60bfd4b43 Enhance Verilog support by adding Vivado BRAM interface handling and updating documentation 
Signed-off-by: Stavros Avramidis <stavros9899@gmail.com>
 2026-10-25 11:28:17 +02:00
purpl3F0x 0c1272e35e Add Verilog parsing and rendering support 
- Introduced `verilog.typ` for parsing Verilog/SystemVerilog source code, supporting both ANSI and non-ANSI port styles.
- Implemented functions to analyze modules, infer AXI4, AXI4-Lite, and AXI4-Stream buses, as well as clock and reset signals.
- Added rendering capabilities for Verilog modules, allowing for visual representation of ports and buses.
- Created a new `gallery/verilog.typ` file to facilitate the drawing of Verilog blocks in diagrams.

Signed-off-by: Stavros Avramidis <stavros9899@gmail.com>
 2026-09-10 12:17:54 +01:00