Klagarge/SEm-ExamMidterm2024
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exercice 3

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This commit is contained in:
Rémi Heredero 2024-03-22 13:48:57 +01:00
parent 8b2f630f7b
commit 4ba38000a8
6 changed files with 2819 additions and 31 deletions
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28
VHD/hdl/ex_24_1_3_entity.vhd Normal file
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@ -0,0 +1,28 @@
-- VHDL Entity VHD.ex_24_1_3.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 09:40:30 03/27/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY ex_24_1_3 IS
GENERIC(
timerBitNb : positive := 8;
testModeBitNb : positive := 1
);
PORT(
testMode : IN std_ulogic;
clock : IN std_ulogic;
reset : IN std_ulogic;
pwmEn : OUT std_ulogic
);
-- Declarations
END ex_24_1_3 ;

26
VHD/hdl/ex_24_1_3_studentVersion.vhd
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@ -1,4 +1,28 @@
architecture studentVersion of ex_24_1_3 is
signal counter : unsigned(timerBitNb-1 downto 0);
begin
pwmEn <= '0';
process(reset, clock) begin
if reset = '1' then
counter <= (others => '0');
elsif rising_edge(clock) then
if testMode = '0' then
counter <= counter - 1;
else
counter <= counter - 2**(timerBitNb - testModeBitNb);
end if;
end if;
end process;
process(counter)
begin
if counter = 0 then
pwmEn <= '1';
else
pwmEn <= '0';
end if;
end process;
end studentVersion;

15
VHD_test/hdl/tb_24_1_3_entity.vhd Normal file
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@ -0,0 +1,15 @@
-- VHDL Entity VHD_test.tb_24_1_3.symbol
--
-- Created:
-- by - remy.borgeat.UNKNOWN (WE10993)
-- at - 15:01:24 20.03.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
ENTITY tb_24_1_3 IS
-- Declarations
END tb_24_1_3 ;

77
VHD_test/hdl/tb_24_1_3_struct.vhd Normal file
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@ -0,0 +1,77 @@
--
-- VHDL Architecture VHD_test.tb_24_1_3.struct
--
-- Created:
-- by - remi.heredero.UNKNOWN (WE2330808)
-- at - 13:45:47 22.03.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
LIBRARY VHD;
ARCHITECTURE struct OF tb_24_1_3 IS
-- Architecture declarations
constant positionBitNb : positive := 8;
constant clockFrequency : real := 100.0E6;
constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
signal sClock : std_uLogic := '1';
signal position_int : integer := 0;
-- Internal signal declarations
SIGNAL clock : std_ulogic;
SIGNAL pwmEn : std_ulogic;
SIGNAL reset : std_ulogic;
SIGNAL testMode : std_ulogic;
-- Component Declarations
COMPONENT ex_24_1_3
GENERIC (
timerBitNb : positive := 8;
testModeBitNb : positive := 1
);
PORT (
testMode : IN std_ulogic ;
clock : IN std_ulogic ;
reset : IN std_ulogic ;
pwmEn : OUT std_ulogic
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : ex_24_1_3 USE ENTITY VHD.ex_24_1_3;
-- pragma synthesis_on
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 eb1
reset <= '1', '0' after 2*clockPeriod;
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after clockPeriod*9/10;
testMode <= '1', '0' after 100*clockPeriod;
-- Instance port mappings.
I_dut : ex_24_1_3
GENERIC MAP (
timerBitNb => 14,
testModeBitNb => 1
)
PORT MAP (
testMode => testMode,
clock => clock,
reset => reset,
pwmEn => pwmEn
);
END struct;

60
VHD_test/hds/tb_24_1_3/struct.bd
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@ -22,7 +22,7 @@ elements [
(GiElement
name "timerBitNb"
type "positive"
value "8"
value "14"
)
(GiElement
name "testModeBitNb"
@ -56,23 +56,23 @@ value " "
)
(vvPair
variable "HDLDir"
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hdl"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd.info"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd.user"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds"
)
(vvPair
variable "appl"
@ -92,27 +92,27 @@ value "%(unit)_config"
)
(vvPair
variable "d"
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3"
)
(vvPair
variable "d_logical"
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3"
)
(vvPair
variable "date"
value "20.03.2024"
value "22.03.2024"
)
(vvPair
variable "day"
value "mer."
value "ven."
)
(vvPair
variable "day_long"
value "mercredi"
value "vendredi"
)
(vvPair
variable "dd"
value "20"
value "22"
)
(vvPair
variable "designName"
@ -140,11 +140,11 @@ value "struct"
)
(vvPair
variable "graphical_source_author"
value "remy.borgeat"
value "remi.heredero"
)
(vvPair
variable "graphical_source_date"
value "20.03.2024"
value "22.03.2024"
)
(vvPair
variable "graphical_source_group"
@ -152,11 +152,11 @@ value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "WE10993"
value "WE2330808"
)
(vvPair
variable "graphical_source_time"
value "15:01:25"
value "13:45:47"
)
(vvPair
variable "group"
@ -164,7 +164,7 @@ value "UNKNOWN"
)
(vvPair
variable "host"
value "WE10993"
value "WE2330808"
)
(vvPair
variable "language"
@ -204,11 +204,11 @@ value "mars"
)
(vvPair
variable "p"
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd"
)
(vvPair
variable "package_name"
@ -276,7 +276,7 @@ value "struct"
)
(vvPair
variable "time"
value "15:01:25"
value "13:45:47"
)
(vvPair
variable "unit"
@ -284,7 +284,7 @@ value "tb_24_1_3"
)
(vvPair
variable "user"
value "remy.borgeat"
value "remi.heredero"
)
(vvPair
variable "version"
@ -328,7 +328,7 @@ va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "44200,54000,56700,55000"
xt "44200,54000,57000,55000"
st "
by %user on %dd %month %year
"
@ -963,9 +963,10 @@ text (MLText
uid 1609,0
va (VaSet
)
xt "46000,38400,58300,40400"
st "timerBitNb = 8 ( positive )
testModeBitNb = 1 ( positive ) "
xt "46000,38400,58500,40400"
st "timerBitNb = 14 ( positive )
testModeBitNb = 1 ( positive )
"
)
header ""
)
@ -973,7 +974,7 @@ elements [
(GiElement
name "timerBitNb"
type "positive"
value "8"
value "14"
)
(GiElement
name "testModeBitNb"
@ -983,7 +984,6 @@ value "1"
]
)
ordering 1
connectByName 1
portVis (PortSigDisplay
sTC 0
)
@ -1250,8 +1250,8 @@ tm "BdCompilerDirectivesTextMgr"
]
associable 1
)
windowSize "168,53,1377,952"
viewArea "-1200,-1200,83166,58226"
windowSize "168,53,1378,952"
viewArea "-1200,-1200,83252,58226"
cachedDiagramExtent "0,0,81000,55000"
pageSetupInfo (PageSetupInfo
ptrCmd "Generic PostScript Printer,winspool,"
@ -1276,7 +1276,7 @@ boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "0,0"
lastUid 1671,0
lastUid 1702,0
defaultCommentText (CommentText
shape (Rectangle
layer 0

2644
VHD_test/hds/tb_24_1_3/struct.bd.bak Normal file
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