Initial commit

VHD_test/hdl/tb_24_1_1_entity.vhd

@@ -0,0 +1,15 @@
+-- VHDL Entity VHD_test.tb_24_1_1.symbol
+--
+-- Created:
+--          by - remy.borgeat.UNKNOWN (WE10993)
+--          at - 15:01:25 20.03.2024
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+
+
+ENTITY tb_24_1_1 IS
+-- Declarations
+
+END tb_24_1_1 ;
+

VHD_test/hdl/tb_24_1_1_struct.vhd

@@ -0,0 +1,96 @@
+--
+-- VHDL Architecture VHD_test.tb_24_1_1.struct
+--
+-- Created:
+--          by - remy.borgeat.UNKNOWN (WE10993)
+--          at - 15:02:54 20.03.2024
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+LIBRARY VHD;
+
+ARCHITECTURE struct OF tb_24_1_1 IS
+
+   -- Architecture declarations
+   constant positionBitNb : positive := 8;
+   
+   constant clockFrequency : real := 100.0E6;
+   constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
+   signal sClock :  std_uLogic := '1';
+   
+   signal position_int : integer := 0;
+
+   -- Internal signal declarations
+   SIGNAL clock    : std_ulogic;
+   SIGNAL en       : std_ulogic;
+   SIGNAL position : unsigned(positionBitNb-1 DOWNTO 0);
+   SIGNAL reset    : std_ulogic;
+   SIGNAL up_down  : std_ulogic;
+
+
+   -- Component Declarations
+   COMPONENT ex_24_1_1
+   GENERIC (
+      counterBitNb : positive := 8
+   );
+   PORT (
+      en       : IN     std_ulogic ;
+      position : OUT    unsigned (counterBitNb-1 DOWNTO 0);
+      up_down  : IN     std_ulogic ;
+      clock    : IN     std_ulogic ;
+      reset    : IN     std_ulogic 
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : ex_24_1_1 USE ENTITY VHD.ex_24_1_1;
+   -- pragma synthesis_on
+
+
+BEGIN
+   -- Architecture concurrent statements
+   -- HDL Embedded Text Block 1 eb1
+   reset <= '1', '0' after 2*clockPeriod;
+   sClock <= not sClock after clockPeriod/2;
+   clock <= transport sClock after clockPeriod*9/10;
+   
+   process
+     constant stepDelay: time := 1 us;
+   begin
+     en <= '0';
+     up_down <= '1';
+     wait for stepDelay;
+     for index in 0 to 10 loop
+     	en <= '1', '0' after clockPeriod;
+       position_int <= position_int + 1;
+       wait for stepDelay;
+     end loop;
+     up_down <= '0';
+     for index in 10 downto 0 loop
+       en <= '1', '0' after clockPeriod;
+       position_int <= position_int - 1;
+       wait for stepDelay;
+     end loop;
+     wait;
+   end process;
+
+
+   -- Instance port mappings.
+   I_dut : ex_24_1_1
+      GENERIC MAP (
+         counterBitNb => positionBitNb
+      )
+      PORT MAP (
+         en       => en,
+         position => position,
+         up_down  => up_down,
+         clock    => clock,
+         reset    => reset
+      );
+
+END struct;

VHD_test/hdl/tb_24_1_2_entity.vhd

@@ -0,0 +1,15 @@
+-- VHDL Entity VHD_test.tb_24_1_2.symbol
+--
+-- Created:
+--          by - remy.borgeat.UNKNOWN (WE10993)
+--          at - 15:01:24 20.03.2024
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+
+
+ENTITY tb_24_1_2 IS
+-- Declarations
+
+END tb_24_1_2 ;
+

VHD_test/hdl/tb_24_1_2_struct.vhd

@@ -0,0 +1,85 @@
+--
+-- VHDL Architecture VHD_test.tb_24_1_2.struct
+--
+-- Created:
+--          by - remy.borgeat.UNKNOWN (WE10993)
+--          at - 15:01:25 20.03.2024
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+LIBRARY VHD;
+
+ARCHITECTURE struct OF tb_24_1_2 IS
+
+   -- Architecture declarations
+   constant pwmFrequency : real := 1.0E6;
+   constant pwmPeriod : time := (1.0/pwmFrequency) * 1 sec;
+   signal sPwm :  std_uLogic := '1';
+
+   -- Internal signal declarations
+   SIGNAL motorOn    : std_ulogic;
+   SIGNAL pwm        : std_ulogic;
+   SIGNAL right_left : std_ulogic;
+   SIGNAL side1      : std_ulogic;
+   SIGNAL side2      : std_ulogic;
+
+
+   -- Component Declarations
+   COMPONENT ex_24_1_2
+   PORT (
+      motorOn    : IN     std_ulogic ;
+      side1      : OUT    std_ulogic ;
+      right_left : IN     std_ulogic ;
+      pwm        : IN     std_ulogic ;
+      side2      : OUT    std_ulogic 
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : ex_24_1_2 USE ENTITY VHD.ex_24_1_2;
+   -- pragma synthesis_on
+
+
+BEGIN
+   -- Architecture concurrent statements
+   -- HDL Embedded Text Block 1 eb1
+   sPwm <= not sPwm after pwmPeriod/2;
+   pwm <= sPwm;
+   
+   process
+     constant testDelay: time := 10 us;
+   begin
+     motorOn <= '0';
+     right_left <= '1';
+     wait for testDelay;
+   
+     motorOn <= '1';
+     wait for testDelay;
+   
+     right_left <= '0';
+     wait for testDelay;
+   
+     motorOn <= '0';
+     wait for testDelay;
+   
+     wait;
+   end process;
+   
+
+
+   -- Instance port mappings.
+   I_dut : ex_24_1_2
+      PORT MAP (
+         motorOn    => motorOn,
+         side1      => side1,
+         right_left => right_left,
+         pwm        => pwm,
+         side2      => side2
+      );
+
+END struct;

VHD_test/hdl/tb_24_1_3_entity.vhg

@@ -0,0 +1,15 @@
+-- VHDL Entity VHD_test.tb_19_1_3.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 09:36:25 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
+--
+
+
+ENTITY tb_19_1_3 IS
+-- Declarations
+
+END tb_19_1_3 ;
+

VHD_test/hdl/tb_24_1_3_struct.vhg

@@ -0,0 +1,77 @@
+--
+-- VHDL Architecture VHD_test.tb_19_1_3.struct
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 12:43:24 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+LIBRARY VHD;
+
+ARCHITECTURE struct OF tb_19_1_3 IS
+
+   -- Architecture declarations
+   constant positionBitNb : positive := 8;
+   
+   constant clockFrequency : real := 100.0E6;
+   constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
+   signal sClock :  std_uLogic := '1';
+   
+   signal position_int : integer := 0;
+
+   -- Internal signal declarations
+   SIGNAL clock    : std_ulogic;
+   SIGNAL pwmEn    : std_ulogic;
+   SIGNAL reset    : std_ulogic;
+   SIGNAL testMode : std_ulogic;
+
+
+   -- Component Declarations
+   COMPONENT ex_19_1_3
+   GENERIC (
+      timerBitNb    : positive := 8;
+      testModeBitNb : positive := 1
+   );
+   PORT (
+      testMode : IN     std_ulogic ;
+      clock    : IN     std_ulogic ;
+      reset    : IN     std_ulogic ;
+      pwmEn    : OUT    std_ulogic 
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : ex_19_1_3 USE ENTITY VHD.ex_19_1_3;
+   -- pragma synthesis_on
+
+
+BEGIN
+   -- Architecture concurrent statements
+   -- HDL Embedded Text Block 1 eb1
+   reset <= '1', '0' after 2*clockPeriod;
+   sClock <= not sClock after clockPeriod/2;
+   clock <= transport sClock after clockPeriod*9/10;
+   
+   testMode <= '1', '0' after 100*clockPeriod;
+
+
+   -- Instance port mappings.
+   I_dut : ex_19_1_3
+      GENERIC MAP (
+         timerBitNb    => 8,
+         testModeBitNb => 1
+      )
+      PORT MAP (
+         testMode => testMode,
+         clock    => clock,
+         reset    => reset,
+         pwmEn    => pwmEn
+      );
+
+END struct;

VHD_test/hdl/tb_24_1_4_entity.vhg

@@ -0,0 +1,15 @@
+-- VHDL Entity VHD_test.tb_19_1_4.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 12:48:46 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
+--
+
+
+ENTITY tb_19_1_4 IS
+-- Declarations
+
+END tb_19_1_4 ;
+

VHD_test/hdl/tb_24_1_4_struct.vhg

@@ -0,0 +1,101 @@
+--
+-- VHDL Architecture VHD_test.tb_19_1_4.struct
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 12:59:54 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+LIBRARY VHD;
+
+ARCHITECTURE struct OF tb_19_1_4 IS
+
+   -- Architecture declarations
+   constant positionBitNb : positive := 8;
+   
+   constant clockFrequency : real := 100.0E6;
+   constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
+   signal sClock :  std_uLogic := '1';
+   
+   signal position_int : integer := 0;
+
+   -- Internal signal declarations
+   SIGNAL A     : std_ulogic;
+   SIGNAL B     : std_ulogic;
+   SIGNAL clock : std_ulogic;
+   SIGNAL dir   : std_ulogic;
+   SIGNAL en    : std_ulogic;
+   SIGNAL reset : std_ulogic;
+
+
+   -- Component Declarations
+   COMPONENT ex_19_1_4
+   PORT (
+      A     : IN     std_ulogic ;
+      B     : IN     std_ulogic ;
+      clock : IN     std_ulogic ;
+      reset : IN     std_ulogic ;
+      en    : OUT    std_ulogic ;
+      dir   : OUT    std_ulogic 
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : ex_19_1_4 USE ENTITY VHD.ex_19_1_4;
+   -- pragma synthesis_on
+
+
+BEGIN
+   -- Architecture concurrent statements
+   -- HDL Embedded Text Block 1 eb1
+   reset <= '1', '0' after 2*clockPeriod;
+   sClock <= not sClock after clockPeriod/2;
+   clock <= transport sClock after clockPeriod*9/10;
+   
+   process
+     constant stepDelay: time := 1 us;
+   begin
+     wait for stepDelay;
+     for index in 0 to 10 loop
+       position_int <= position_int + 1;
+       wait for stepDelay;
+     end loop;
+     for index in 10 downto 0 loop
+       position_int <= position_int - 1;
+       wait for stepDelay;
+     end loop;
+     wait;
+   end process;
+   
+   process(position_int)
+   begin
+     case to_integer(to_unsigned(position_int, 2)) is
+       when 0 => A <= '0'; B <= '0';
+       when 1 => A <= '1'; B <= '0';
+       when 2 => A <= '1'; B <= '1';
+       when 3 => A <= '0'; B <= '1';
+       when others => null;
+     end case;
+   end process;
+   
+   
+
+
+   -- Instance port mappings.
+   I_dut : ex_19_1_4
+      PORT MAP (
+         A     => A,
+         B     => B,
+         clock => clock,
+         reset => reset,
+         en    => en,
+         dir   => dir
+      );
+
+END struct;

VHD_test/hdl/tb_24_1_5_entity.vhg

@@ -0,0 +1,15 @@
+-- VHDL Entity VHD_test.tb_19_1_5.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:03:49 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
+--
+
+
+ENTITY tb_19_1_5 IS
+-- Declarations
+
+END tb_19_1_5 ;
+

VHD_test/hdl/tb_24_1_5_struct.vhg

@@ -0,0 +1,94 @@
+--
+-- VHDL Architecture VHD_test.tb_19_1_5.struct
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:50:24 03/27/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+LIBRARY VHD;
+
+ARCHITECTURE struct OF tb_19_1_5 IS
+
+   -- Architecture declarations
+   constant speedBitNb : positive := 8;
+   
+   constant clockFrequency : real := 100.0E6;
+   constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
+   signal sClock :  std_uLogic := '1';
+   
+   signal position_int : integer := 0;
+
+   -- Internal signal declarations
+   SIGNAL clock : std_ulogic;
+   SIGNAL done  : std_ulogic;
+   SIGNAL reset : std_ulogic;
+   SIGNAL speed : unsigned(speedBitNb-1 DOWNTO 0);
+   SIGNAL start : std_ulogic;
+
+
+   -- Component Declarations
+   COMPONENT ex_19_1_5
+   GENERIC (
+      speedBitNb : positive
+   );
+   PORT (
+      start : IN     std_ulogic ;
+      clock : IN     std_ulogic ;
+      reset : IN     std_ulogic ;
+      done  : OUT    std_ulogic ;
+      speed : OUT    unsigned (speedBitNb-1 DOWNTO 0)
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : ex_19_1_5 USE ENTITY VHD.ex_19_1_5;
+   -- pragma synthesis_on
+
+
+BEGIN
+   -- Architecture concurrent statements
+   -- HDL Embedded Text Block 1 eb1
+   reset <= '1', '0' after 2*clockPeriod;
+   sClock <= not sClock after clockPeriod/2;
+   clock <= transport sClock after clockPeriod*9/10;
+   
+   process
+     constant testDelay: time := 2**(speedBitNb/2+3) * clockPeriod;
+   begin
+     start <= '0';
+   
+     wait for testDelay;
+     start <= '1', '0' after clockPeriod;
+   
+     wait for testDelay;
+     start <= '1', '0' after clockPeriod;
+   
+     wait;
+   end process;
+   
+   
+   
+   
+
+
+   -- Instance port mappings.
+   I_dut : ex_19_1_5
+      GENERIC MAP (
+         speedBitNb => speedBitNb
+      )
+      PORT MAP (
+         start => start,
+         clock => clock,
+         reset => reset,
+         done  => done,
+         speed => speed
+      );
+
+END struct;

VHD_test/hds/.hdlsidedata/_tb_18_1_1_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_1_1_struct.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_1_2_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_1_2_struct.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_1_4_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_1_4_struct.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_1_5_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_1_5_struct.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_2_1_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_2_1_struct.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_2_2_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_2_2_struct.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_2_3_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_2_3_struct.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_2_4_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_2_4_struct.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_2_5_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_18_2_5_struct.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_19_1_1_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_19_1_1_struct.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_19_1_2_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_19_1_2_struct.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_19_1_3_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_19_1_3_struct.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_19_1_4_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_19_1_4_struct.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_19_1_5_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_19_1_5_struct.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

VHD_test/hds/.hdlsidedata/_tb_24_1_1_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

VHD_test/hds/.hdlsidedata/_tb_24_1_1_struct.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

VHD_test/hds/.hdlsidedata/_tb_24_1_2_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

VHD_test/hds/.hdlsidedata/_tb_24_1_2_struct.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

VHD_test/hds/.hdlsidedata/_tb_24_1_3_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

VHD_test/hds/.hdlsidedata/_tb_24_1_3_struct.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

VHD_test/hds/.hdlsidedata/_tb_24_1_4_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

VHD_test/hds/.hdlsidedata/_tb_24_1_4_struct.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

VHD_test/hds/.hdlsidedata/_tb_24_1_5_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

VHD_test/hds/.hdlsidedata/_tb_24_1_5_struct.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

VHD_test/hds/.xrf/tb_24_1_1_entity.xrf

@@ -0,0 +1,12 @@
+DESIGN tb_24_1_1
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN tb_24_1_1
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN tb_24_1_1
+VIEW symbol.sb
+GRAPHIC 1,0 11 0 
+DESIGN tb_24_1_1
+VIEW symbol.sb
+GRAPHIC 1,0 12 0 

VHD_test/hds/.xrf/tb_24_1_1_struct.xrf

@@ -0,0 +1,104 @@
+DESIGN tb_24_1_1
+VIEW struct.bd
+NO_GRAPHIC 0
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 142,0 9 0 
+DESIGN tb_24_1_1
+VIEW struct.bd
+NO_GRAPHIC 12
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 0,0 15 2 
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 1,0 18 0 
+DESIGN tb_24_1_1
+VIEW struct.bd
+NO_GRAPHIC 18
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 1122,0 27 0 
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 1272,0 28 0 
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 1098,0 29 0 
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 1130,0 30 0 
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 1280,0 31 0 
+DESIGN tb_24_1_1
+VIEW struct.bd
+NO_GRAPHIC 32
+DESIGN tb_24_1_1
+VIEW struct.bd
+NO_GRAPHIC 33
+LIBRARY VHD
+DESIGN ex_24_1_1
+VIEW student@version
+GRAPHIC 1659,0 35 0 
+DESIGN ex_24_1_1
+VIEW symbol.sb
+GRAPHIC 14,0 36 1 
+DESIGN ex_24_1_1
+VIEW symbol.sb
+GRAPHIC 57,0 40 0 
+DESIGN ex_24_1_1
+VIEW symbol.sb
+GRAPHIC 89,0 41 0 
+DESIGN ex_24_1_1
+VIEW symbol.sb
+GRAPHIC 262,0 42 0 
+DESIGN ex_24_1_1
+VIEW symbol.sb
+GRAPHIC 267,0 43 0 
+DESIGN ex_24_1_1
+VIEW symbol.sb
+GRAPHIC 272,0 44 0 
+LIBRARY VHD_test
+DESIGN tb_24_1_1
+VIEW struct.bd
+NO_GRAPHIC 47
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 1659,0 50 0 
+DESIGN tb_24_1_1
+VIEW struct.bd
+NO_GRAPHIC 53
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 445,0 56 0 
+DESIGN tb_24_1_1
+VIEW struct.bd
+NO_GRAPHIC 80
+DESIGN tb_24_1_1
+VIEW struct.bd
+NO_GRAPHIC 81
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 1659,0 83 0 
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 1666,0 84 1 
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 1274,0 88 0 
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 1100,0 89 0 
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 1282,0 90 0 
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 1124,0 91 0 
+DESIGN tb_24_1_1
+VIEW struct.bd
+GRAPHIC 1132,0 92 0 
+DESIGN tb_24_1_1
+VIEW struct.bd
+NO_GRAPHIC 95

VHD_test/hds/.xrf/tb_24_1_2_entity.xrf

@@ -0,0 +1,12 @@
+DESIGN tb_24_1_2
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN tb_24_1_2
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN tb_24_1_2
+VIEW symbol.sb
+GRAPHIC 1,0 11 0 
+DESIGN tb_24_1_2
+VIEW symbol.sb
+GRAPHIC 1,0 12 0 

VHD_test/hds/.xrf/tb_24_1_2_struct.xrf

@@ -0,0 +1,98 @@
+DESIGN tb_24_1_2
+VIEW struct.bd
+NO_GRAPHIC 0
+DESIGN tb_24_1_2
+VIEW struct.bd
+GRAPHIC 142,0 9 0 
+DESIGN tb_24_1_2
+VIEW struct.bd
+NO_GRAPHIC 12
+DESIGN tb_24_1_2
+VIEW struct.bd
+GRAPHIC 0,0 15 2 
+DESIGN tb_24_1_2
+VIEW struct.bd
+GRAPHIC 1,0 18 0 
+DESIGN tb_24_1_2
+VIEW struct.bd
+NO_GRAPHIC 18
+DESIGN tb_24_1_2
+VIEW struct.bd
+GRAPHIC 1370,0 23 0 
+DESIGN tb_24_1_2
+VIEW struct.bd
+GRAPHIC 1386,0 24 0 
+DESIGN tb_24_1_2
+VIEW struct.bd
+GRAPHIC 1378,0 25 0 
+DESIGN tb_24_1_2
+VIEW struct.bd
+GRAPHIC 1362,0 26 0 
+DESIGN tb_24_1_2
+VIEW struct.bd
+GRAPHIC 1354,0 27 0 
+DESIGN tb_24_1_2
+VIEW struct.bd
+NO_GRAPHIC 28
+DESIGN tb_24_1_2
+VIEW struct.bd
+NO_GRAPHIC 29
+LIBRARY VHD
+DESIGN ex_24_1_2
+VIEW student@version
+GRAPHIC 1519,0 31 0 
+DESIGN ex_24_1_2
+VIEW symbol.sb
+GRAPHIC 57,0 33 0 
+DESIGN ex_24_1_2
+VIEW symbol.sb
+GRAPHIC 89,0 34 0 
+DESIGN ex_24_1_2
+VIEW symbol.sb
+GRAPHIC 262,0 35 0 
+DESIGN ex_24_1_2
+VIEW symbol.sb
+GRAPHIC 267,0 36 0 
+DESIGN ex_24_1_2
+VIEW symbol.sb
+GRAPHIC 352,0 37 0 
+LIBRARY VHD_test
+DESIGN tb_24_1_2
+VIEW struct.bd
+NO_GRAPHIC 40
+DESIGN tb_24_1_2
+VIEW struct.bd
+GRAPHIC 1519,0 43 0 
+DESIGN tb_24_1_2
+VIEW struct.bd
+NO_GRAPHIC 46
+DESIGN tb_24_1_2
+VIEW struct.bd
+GRAPHIC 445,0 49 0 
+DESIGN tb_24_1_2
+VIEW struct.bd
+NO_GRAPHIC 72
+DESIGN tb_24_1_2
+VIEW struct.bd
+NO_GRAPHIC 73
+DESIGN tb_24_1_2
+VIEW struct.bd
+GRAPHIC 1519,0 75 0 
+DESIGN tb_24_1_2
+VIEW struct.bd
+GRAPHIC 1372,0 77 0 
+DESIGN tb_24_1_2
+VIEW struct.bd
+GRAPHIC 1364,0 78 0 
+DESIGN tb_24_1_2
+VIEW struct.bd
+GRAPHIC 1380,0 79 0 
+DESIGN tb_24_1_2
+VIEW struct.bd
+GRAPHIC 1388,0 80 0 
+DESIGN tb_24_1_2
+VIEW struct.bd
+GRAPHIC 1356,0 81 0 
+DESIGN tb_24_1_2
+VIEW struct.bd
+NO_GRAPHIC 84

VHD_test/hds/.xrf/tb_24_1_3_entity.xrf

@@ -0,0 +1,12 @@
+DESIGN tb_24_1_3
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN tb_24_1_3
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN tb_24_1_3
+VIEW symbol.sb
+GRAPHIC 1,0 11 0 
+DESIGN tb_24_1_3
+VIEW symbol.sb
+GRAPHIC 1,0 12 0 

VHD_test/hds/.xrf/tb_24_1_3_struct.xrf

@@ -0,0 +1,95 @@
+DESIGN tb_24_1_3
+VIEW struct.bd
+NO_GRAPHIC 0
+DESIGN tb_24_1_3
+VIEW struct.bd
+GRAPHIC 142,0 9 0 
+DESIGN tb_24_1_3
+VIEW struct.bd
+NO_GRAPHIC 12
+DESIGN tb_24_1_3
+VIEW struct.bd
+GRAPHIC 0,0 15 2 
+DESIGN tb_24_1_3
+VIEW struct.bd
+GRAPHIC 1,0 18 0 
+DESIGN tb_24_1_3
+VIEW struct.bd
+NO_GRAPHIC 18
+DESIGN tb_24_1_3
+VIEW struct.bd
+GRAPHIC 1122,0 27 0 
+DESIGN tb_24_1_3
+VIEW struct.bd
+GRAPHIC 1503,0 28 0 
+DESIGN tb_24_1_3
+VIEW struct.bd
+GRAPHIC 1130,0 29 0 
+DESIGN tb_24_1_3
+VIEW struct.bd
+GRAPHIC 1511,0 30 0 
+DESIGN tb_24_1_3
+VIEW struct.bd
+NO_GRAPHIC 31
+DESIGN tb_24_1_3
+VIEW struct.bd
+NO_GRAPHIC 32
+LIBRARY VHD
+DESIGN ex_24_1_3
+VIEW student@version
+GRAPHIC 1601,0 34 0 
+DESIGN ex_24_1_3
+VIEW symbol.sb
+GRAPHIC 14,0 35 1 
+DESIGN ex_24_1_3
+VIEW symbol.sb
+GRAPHIC 262,0 40 0 
+DESIGN ex_24_1_3
+VIEW symbol.sb
+GRAPHIC 267,0 41 0 
+DESIGN ex_24_1_3
+VIEW symbol.sb
+GRAPHIC 272,0 42 0 
+DESIGN ex_24_1_3
+VIEW symbol.sb
+GRAPHIC 400,0 43 0 
+LIBRARY VHD_test
+DESIGN tb_24_1_3
+VIEW struct.bd
+NO_GRAPHIC 46
+DESIGN tb_24_1_3
+VIEW struct.bd
+GRAPHIC 1601,0 49 0 
+DESIGN tb_24_1_3
+VIEW struct.bd
+NO_GRAPHIC 52
+DESIGN tb_24_1_3
+VIEW struct.bd
+GRAPHIC 445,0 55 0 
+DESIGN tb_24_1_3
+VIEW struct.bd
+NO_GRAPHIC 61
+DESIGN tb_24_1_3
+VIEW struct.bd
+NO_GRAPHIC 62
+DESIGN tb_24_1_3
+VIEW struct.bd
+GRAPHIC 1601,0 64 0 
+DESIGN tb_24_1_3
+VIEW struct.bd
+GRAPHIC 1608,0 65 1 
+DESIGN tb_24_1_3
+VIEW struct.bd
+GRAPHIC 1513,0 70 0 
+DESIGN tb_24_1_3
+VIEW struct.bd
+GRAPHIC 1124,0 71 0 
+DESIGN tb_24_1_3
+VIEW struct.bd
+GRAPHIC 1132,0 72 0 
+DESIGN tb_24_1_3
+VIEW struct.bd
+GRAPHIC 1505,0 73 0 
+DESIGN tb_24_1_3
+VIEW struct.bd
+NO_GRAPHIC 76

VHD_test/hds/.xrf/tb_24_1_4_entity.xrf

@@ -0,0 +1,12 @@
+DESIGN tb_24_1_4
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN tb_24_1_4
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN tb_24_1_4
+VIEW symbol.sb
+GRAPHIC 1,0 11 0 
+DESIGN tb_24_1_4
+VIEW symbol.sb
+GRAPHIC 1,0 12 0 

VHD_test/hds/.xrf/tb_24_1_4_struct.xrf

@@ -0,0 +1,107 @@
+DESIGN tb_24_1_4
+VIEW struct.bd
+NO_GRAPHIC 0
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 142,0 9 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+NO_GRAPHIC 12
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 0,0 15 2 
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 1,0 18 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+NO_GRAPHIC 18
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 1106,0 25 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 1114,0 26 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 1122,0 27 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 1280,0 28 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 1288,0 29 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 1130,0 30 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+NO_GRAPHIC 31
+DESIGN tb_24_1_4
+VIEW struct.bd
+NO_GRAPHIC 32
+LIBRARY VHD
+DESIGN ex_24_1_4
+VIEW student@version
+GRAPHIC 1495,0 34 0 
+DESIGN ex_24_1_4
+VIEW symbol.sb
+GRAPHIC 57,0 36 0 
+DESIGN ex_24_1_4
+VIEW symbol.sb
+GRAPHIC 262,0 37 0 
+DESIGN ex_24_1_4
+VIEW symbol.sb
+GRAPHIC 267,0 38 0 
+DESIGN ex_24_1_4
+VIEW symbol.sb
+GRAPHIC 272,0 39 0 
+DESIGN ex_24_1_4
+VIEW symbol.sb
+GRAPHIC 329,0 40 0 
+DESIGN ex_24_1_4
+VIEW symbol.sb
+GRAPHIC 334,0 41 0 
+LIBRARY VHD_test
+DESIGN tb_24_1_4
+VIEW struct.bd
+NO_GRAPHIC 44
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 1495,0 47 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+NO_GRAPHIC 50
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 445,0 53 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+NO_GRAPHIC 85
+DESIGN tb_24_1_4
+VIEW struct.bd
+NO_GRAPHIC 86
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 1495,0 88 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 1108,0 90 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 1116,0 91 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 1124,0 92 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 1132,0 93 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 1290,0 94 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+GRAPHIC 1282,0 95 0 
+DESIGN tb_24_1_4
+VIEW struct.bd
+NO_GRAPHIC 98

VHD_test/hds/.xrf/tb_24_1_5_entity.xrf

@@ -0,0 +1,12 @@
+DESIGN tb_24_1_5
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN tb_24_1_5
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN tb_24_1_5
+VIEW symbol.sb
+GRAPHIC 1,0 11 0 
+DESIGN tb_24_1_5
+VIEW symbol.sb
+GRAPHIC 1,0 12 0 

VHD_test/hds/.xrf/tb_24_1_5_struct.xrf

@@ -0,0 +1,104 @@
+DESIGN tb_24_1_5
+VIEW struct.bd
+NO_GRAPHIC 0
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 142,0 9 0 
+DESIGN tb_24_1_5
+VIEW struct.bd
+NO_GRAPHIC 12
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 0,0 15 2 
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 1,0 18 0 
+DESIGN tb_24_1_5
+VIEW struct.bd
+NO_GRAPHIC 18
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 1122,0 27 0 
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 1498,0 28 0 
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 1130,0 29 0 
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 1506,0 30 0 
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 1514,0 31 0 
+DESIGN tb_24_1_5
+VIEW struct.bd
+NO_GRAPHIC 32
+DESIGN tb_24_1_5
+VIEW struct.bd
+NO_GRAPHIC 33
+LIBRARY VHD
+DESIGN ex_24_1_5
+VIEW student@version
+GRAPHIC 1581,0 35 0 
+DESIGN ex_24_1_5
+VIEW symbol.sb
+GRAPHIC 14,0 36 1 
+DESIGN ex_24_1_5
+VIEW symbol.sb
+GRAPHIC 262,0 40 0 
+DESIGN ex_24_1_5
+VIEW symbol.sb
+GRAPHIC 267,0 41 0 
+DESIGN ex_24_1_5
+VIEW symbol.sb
+GRAPHIC 272,0 42 0 
+DESIGN ex_24_1_5
+VIEW symbol.sb
+GRAPHIC 334,0 43 0 
+DESIGN ex_24_1_5
+VIEW symbol.sb
+GRAPHIC 390,0 44 0 
+LIBRARY VHD_test
+DESIGN tb_24_1_5
+VIEW struct.bd
+NO_GRAPHIC 47
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 1581,0 50 0 
+DESIGN tb_24_1_5
+VIEW struct.bd
+NO_GRAPHIC 53
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 445,0 56 0 
+DESIGN tb_24_1_5
+VIEW struct.bd
+NO_GRAPHIC 78
+DESIGN tb_24_1_5
+VIEW struct.bd
+NO_GRAPHIC 79
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 1581,0 81 0 
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 1588,0 82 1 
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 1516,0 86 0 
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 1124,0 87 0 
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 1132,0 88 0 
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 1500,0 89 0 
+DESIGN tb_24_1_5
+VIEW struct.bd
+GRAPHIC 1508,0 90 0 
+DESIGN tb_24_1_5
+VIEW struct.bd
+NO_GRAPHIC 93

VHD_test/hds/_tb_24_1_1._epf

@@ -0,0 +1,2 @@
+DEFAULT_FILE atom tb_24_1_1/struct.bd
+DEFAULT_ARCHITECTURE atom struct

VHD_test/hds/_tb_24_1_2._epf

@@ -0,0 +1,2 @@
+DEFAULT_FILE atom tb_24_1_2/struct.bd
+DEFAULT_ARCHITECTURE atom struct

VHD_test/hds/_tb_24_1_3._epf

@@ -0,0 +1,2 @@
+DEFAULT_FILE atom tb_24_1_3/struct.bd
+DEFAULT_ARCHITECTURE atom struct

VHD_test/hds/_tb_24_1_4._epf

@@ -0,0 +1,2 @@
+DEFAULT_FILE atom tb_24_1_4/struct.bd
+DEFAULT_ARCHITECTURE atom struct

VHD_test/hds/_tb_24_1_5._epf

@@ -0,0 +1,2 @@
+DEFAULT_FILE atom tb_24_1_5/struct.bd
+DEFAULT_ARCHITECTURE atom struct

VHD_test/hds/tb_24_1_1/_struct.bd._fpf

@@ -0,0 +1,16 @@
+ARCHITECTURES list {
+ {tb_18_2_1 struct} list {
+  TASK_SETTINGS list {
+   PLUGIN_SETTINGS list {
+    ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_18_2_1.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0}
+   }
+  }
+ }
+ {tb_24_1_1 struct} list {
+  TASK_SETTINGS list {
+   PLUGIN_SETTINGS list {
+    ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_19_1_1.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0}
+   }
+  }
+ }
+}

VHD_test/hds/tb_24_1_1/default_view

@@ -0,0 +1,2 @@
+DefaultView = struct.bd
+Top = false

VHD_test/hds/tb_24_1_2/_struct.bd._fpf

@@ -0,0 +1,23 @@
+ARCHITECTURES list {
+ {tb_18_2_1 struct} list {
+  TASK_SETTINGS list {
+   PLUGIN_SETTINGS list {
+    ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_18_2_1.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0}
+   }
+  }
+ }
+ {tb_19_1_1 struct} list {
+  TASK_SETTINGS list {
+   PLUGIN_SETTINGS list {
+    ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_19_1_1.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0}
+   }
+  }
+ }
+ {tb_24_1_2 struct} list {
+  TASK_SETTINGS list {
+   PLUGIN_SETTINGS list {
+    ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_19_1_2.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0}
+   }
+  }
+ }
+}

VHD_test/hds/tb_24_1_2/default_view

@@ -0,0 +1,2 @@
+DefaultView = struct.bd
+Top = false

VHD_test/hds/tb_24_1_3/_struct.bd._fpf

@@ -0,0 +1,23 @@
+ARCHITECTURES list {
+ {tb_18_2_1 struct} list {
+  TASK_SETTINGS list {
+   PLUGIN_SETTINGS list {
+    ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_18_2_1.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0}
+   }
+  }
+ }
+ {tb_19_1_1 struct} list {
+  TASK_SETTINGS list {
+   PLUGIN_SETTINGS list {
+    ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_19_1_1.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0}
+   }
+  }
+ }
+ {tb_24_1_3 struct} list {
+  TASK_SETTINGS list {
+   PLUGIN_SETTINGS list {
+    ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_19_1_3.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0}
+   }
+  }
+ }
+}

VHD_test/hds/tb_24_1_3/default_view

@@ -0,0 +1,2 @@
+DefaultView = struct.bd
+Top = false

VHD_test/hds/tb_24_1_4/_struct.bd._fpf

@@ -0,0 +1,16 @@
+ARCHITECTURES list {
+ {tb_18_2_1 struct} list {
+  TASK_SETTINGS list {
+   PLUGIN_SETTINGS list {
+    ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_18_2_1.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0}
+   }
+  }
+ }
+ {tb_24_1_4 struct} list {
+  TASK_SETTINGS list {
+   PLUGIN_SETTINGS list {
+    ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_19_1_4.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0}
+   }
+  }
+ }
+}

VHD_test/hds/tb_24_1_4/default_view

@@ -0,0 +1,2 @@
+DefaultView = struct.bd
+Top = false

VHD_test/hds/tb_24_1_5/_struct.bd._fpf

@@ -0,0 +1,23 @@
+ARCHITECTURES list {
+ {tb_18_2_1 struct} list {
+  TASK_SETTINGS list {
+   PLUGIN_SETTINGS list {
+    ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_18_2_1.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0}
+   }
+  }
+ }
+ {tb_19_1_4 struct} list {
+  TASK_SETTINGS list {
+   PLUGIN_SETTINGS list {
+    ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_19_1_4.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0}
+   }
+  }
+ }
+ {tb_24_1_5 struct} list {
+  TASK_SETTINGS list {
+   PLUGIN_SETTINGS list {
+    ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_19_1_5.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0}
+   }
+  }
+ }
+}

VHD_test/hds/tb_24_1_5/default_view

@@ -0,0 +1,2 @@
+DefaultView = struct.bd
+Top = false