Initial commit

Libs/RiscV/HEIRV32/MultiCycle/hdl/instrDecoder_rtl.vhd

@@ -0,0 +1,18 @@
+
+ARCHITECTURE rtl OF instrDecoder IS
+BEGIN
+
+    decode : process(op)
+    begin
+        case op is
+            when "0000011" => immSrc <= "00"; -- lw
+            when "0100011" => immSrc <= "01"; -- sw
+            when "0110011" => immSrc <= "--"; -- R-type
+            when "1100011" => immSrc <= "10"; -- beq
+            when "0010011" => immSrc <= "00"; -- l-type ALU
+            when "1101111" => immSrc <= "11"; -- jal
+            when others => immSrc <= "--"; -- unknwon
+        end case;
+    end process decode;
+
+END ARCHITECTURE rtl;

Libs/RiscV/HEIRV32/MultiCycle/hdl/instructionForwarder_rtl.vhd

@@ -0,0 +1,26 @@
+
+ARCHITECTURE rtl OF instructionForwarder IS
+    signal lvec_irMem : std_ulogic_vector(readData'range);
+BEGIN
+
+--    forwardIR : process(rst, clk)
+--    begin
+--        if rst = '1' then
+--            lvec_irMem <= (others => '0');
+--        elsif rising_edge(clk) then
+--            if en = '1' and IRWrite = '1' then
+--                lvec_irMem <= readData;
+--            end if;
+--        end if;
+--    end process forwardIR;
+
+    forwardIR : process(readData, irWrite)
+    begin
+        if irWrite = '1' then
+            lvec_irMem <= readData;
+        end if;
+    end process forwardIR;
+
+    instruction <= lvec_irMem;
+
+END ARCHITECTURE rtl;

Libs/RiscV/HEIRV32/MultiCycle/hds/.hdlsidedata/_aluDecoder_rtl.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/RiscV/HEIRV32/MultiCycle/hds/.hdlsidedata/_instrDecoder_rtl.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/RiscV/HEIRV32/MultiCycle/hds/.hdlsidedata/_instructionForwarder_rtl.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/RiscV/HEIRV32/MultiCycle/hds/.hdlsidedata/_mainfsm_fsm.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/RiscV/HEIRV32/MultiCycle/hds/_controlunit._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom struct
+DEFAULT_FILE atom control@unit/struct.bd

Libs/RiscV/HEIRV32/MultiCycle/hds/_heirv32_mc._epf

@@ -0,0 +1,3 @@
+TOP_MARKER atom 1
+DEFAULT_FILE atom heirv32_mc/struct.bd
+DEFAULT_ARCHITECTURE atom struct

Libs/RiscV/HEIRV32/MultiCycle/hds/_instrdecoder._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom instrDecoder_rtl.vhd

Libs/RiscV/HEIRV32/MultiCycle/hds/_instructiondatamemory._epf

@@ -0,0 +1,2 @@
+DEFAULT_FILE atom instruction@data@memory/struct.bd
+DEFAULT_ARCHITECTURE atom struct

Libs/RiscV/HEIRV32/MultiCycle/hds/_instructionforwarder._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom instructionForwarder_rtl.vhd

Libs/RiscV/HEIRV32/MultiCycle/hds/_mainfsm._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom fsm
+DEFAULT_FILE atom main@f@s@m/fsm.sm

Libs/RiscV/HEIRV32/SingleCycle/hdl/dataMemory_rtl.vhd

@@ -0,0 +1,32 @@
+
+ARCHITECTURE rtl OF dataMemory IS
+
+  -- Bank of data
+  type t_dataBank is array (0 to (2**g_memoryNbBits)-1) of
+    std_ulogic_vector(g_dataWidth-1 downto 0);
+  -- A bank of data
+  signal larr_data: t_dataBank;
+
+BEGIN
+
+  process(rst, clk)
+  begin
+    if rst = '1' then
+      larr_data <= (others => (others => '0')) after g_tMemWr;
+    elsif rising_edge(clk) then
+      if en = '1' and writeEn = '1' then
+        -- skip the two last bits (since we do only +4)
+        larr_data(to_integer(unsigned(
+          address(g_memoryNbBits+1 downto 2)
+        ))) <= writeData after (g_tMemWr + g_tSetup);
+      end if;
+    end if;
+  end process;
+
+  -- Comb. read
+    -- skip the two last bits (since we do only +4)
+  readData <= larr_data(to_integer(unsigned(
+    address(g_memoryNbBits+1 downto 2)
+  ))) after g_tMemRd;
+
+END ARCHITECTURE rtl;

Libs/RiscV/HEIRV32/SingleCycle/hdl/instrMemory_bin.vhd

@@ -0,0 +1,34 @@
+USE std.textio.all;
+
+ARCHITECTURE bin OF instrMemory IS
+
+  -- Instructions type
+  type t_instrBank is array (g_memoryNbBits-1 downto 0) of
+    std_ulogic_vector(g_dataWidth-1 downto 0);
+
+  -- Define function to create initvalue signal
+  impure function ReadRamContentFromFile(ramContentFilenAme : in string) return t_instrBank is
+    FILE     ramContentFile     : text is in ramContentFilenAme;
+    variable ramContentFileLine : line;
+    variable ramContent         : t_instrBank;
+  begin
+    for i in t_instrBank'range loop
+      readline(ramContentFile, ramContentFileLine);
+      read(ramContentFileLine, ramContent(i));
+    end loop;
+    return ramContent;
+  end function;
+
+  -- Program
+  constant larr_instr : t_instrBank := ReadRamContentFromFile(g_programFile);
+
+BEGIN
+
+  -- Comb. read
+  process(PC)
+  begin
+    -- skip the two last bits (since we do only +4)
+    instruction <= larr_instr(to_integer(PC(g_memoryNbBits+1 downto 2)));
+  end process;
+  
+END ARCHITECTURE bin;

Libs/RiscV/HEIRV32/SingleCycle/hdl/instrMemory_hex.vhd

@@ -0,0 +1,36 @@
+library ieee;
+  use std.textio.all;
+  use ieee.std_logic_textio.all;
+
+ARCHITECTURE hex OF instrMemory IS
+
+  -- Instructions type
+  type t_instrBank is array (0 to (2**g_memoryNbBits)-1) of
+    std_ulogic_vector(g_dataWidth-1 downto 0);
+
+  -- Define function to create initvalue signal
+  impure function ReadRamContentFromFile(ramContentFilenAme : in string) return t_instrBank is
+    FILE     ramContentFile     : text is in ramContentFilenAme;
+    variable ramContentFileLine : line;
+    variable ramContent         : t_instrBank;
+  begin
+    for i in t_instrBank'range loop
+      readline(ramContentFile, ramContentFileLine);
+      HREAD(ramContentFileLine, ramContent(i));
+    end loop;
+    return ramContent;
+  end function;
+
+  -- Program
+  constant larr_instr : t_instrBank := ReadRamContentFromFile(g_programFile);
+
+BEGIN
+
+  -- Comb. read
+  process(PC)
+  begin
+    -- skip the two last bits (since we do only +4)
+    instruction <= larr_instr(to_integer(PC(g_memoryNbBits+1 downto 2))) after g_tMemRd;
+  end process;
+  
+END ARCHITECTURE hex;

Libs/RiscV/HEIRV32/SingleCycle/hdl/mainDecoder_rtl.vhd

@@ -0,0 +1,24 @@
+
+ARCHITECTURE rtl OF mainDecoder IS
+
+  signal lvec_controls : std_ulogic_vector(10 downto 0);
+
+BEGIN
+
+  process(op)
+  begin
+    case op is
+      when "0000011" => lvec_controls <= "10010010000"; -- lw
+      when "0100011" => lvec_controls <= "00111000000"; -- sw
+      when "0110011" => lvec_controls <= "1--00000100"; -- R-type
+      when "1100011" => lvec_controls <= "01000001010"; -- beq
+      when "0010011" => lvec_controls <= "10010000100"; -- I-type ALU
+      when "1101111" => lvec_controls <= "11100100001"; -- jal
+      when others    => lvec_controls <= "-----------"; -- not valid
+    end case;
+  end process;
+
+  (regwrite, immSrc(1), immSrc(0), ALUSrc, memWrite, resultSrc(1), resultSrc(0),
+    branch, ALUOp(1), ALUOp(0), jump) <= lvec_controls after g_tDec;
+
+END ARCHITECTURE rtl;

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_controlunit_masterversion.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_dataMemory_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_bin.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_hex.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_instrMemory_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_mainDecoder_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/.hdlsidedata/_rtl_instrMemory.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/SingleCycle/hds/_bin._epf

@@ -0,0 +1,2 @@
+DEFAULT_FILE atom rtl_instrMemory.vhd
+DEFAULT_ARCHITECTURE atom instrMemory

Libs/RiscV/HEIRV32/SingleCycle/hds/_controlunit._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom masterVersion
+DEFAULT_FILE atom control@unit/master@version.bd

Libs/RiscV/HEIRV32/SingleCycle/hds/_datamemory._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom dataMemory_rtl.vhd

Libs/RiscV/HEIRV32/SingleCycle/hds/_heirv32_sc._epf

@@ -0,0 +1,3 @@
+TOP_MARKER atom 1
+DEFAULT_FILE atom heirv32_sc/struct.bd
+DEFAULT_ARCHITECTURE atom struct

Libs/RiscV/HEIRV32/SingleCycle/hds/_instrmemory._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom hex
+DEFAULT_FILE atom instrMemory_hex.vhd

Libs/RiscV/HEIRV32/SingleCycle/hds/_maindecoder._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom mainDecoder_rtl.vhd

Libs/RiscV/HEIRV32/hdl/ALU_rtl.vhd

@@ -0,0 +1,40 @@
+-- Risc-V ed. 2022 page 250 (pdf page 273)
+
+ARCHITECTURE rtl OF ALU IS
+
+    signal lvec_res : std_ulogic_vector(res'range);
+	signal lsig_zero : std_ulogic;
+
+BEGIN
+
+    lsig_zero <= '1' when lvec_res = (lvec_res'range => '0') else '0';
+	zero <= lsig_zero after g_tALU;
+    res <= lvec_res after g_tALU;
+
+    alu : process(srcA, srcB, ctrl)
+    begin
+        case ctrl is
+            when "000" => -- add
+                lvec_res <= std_ulogic_vector(resize(
+                    unsigned(srcA) + unsigned(srcB), lvec_res'length
+                ));
+            when "001" => -- substract
+                lvec_res <= std_ulogic_vector(resize(
+                    unsigned(srcA) - unsigned(srcB), lvec_res'length
+                ));
+            when "010" => -- AND
+                lvec_res <= srcA and srcB;
+            when "011" => -- OR
+                lvec_res <= srcA or srcB;
+            when "101" => -- SLT
+                if srcA < srcB then
+                    lvec_res <= (lvec_res'high downto 1 => '0') & '1';
+                else
+                    lvec_res <= (lvec_res'high downto 1 => '0') & '0';
+                end if;
+            when others => -- unknown
+                lvec_res <= (others => '-');
+        end case;
+    end process alu;
+
+END ARCHITECTURE rtl;

Libs/RiscV/HEIRV32/hdl/aluDecoder_rtl.vhd

@@ -0,0 +1,27 @@
+
+ARCHITECTURE rtl OF aluDecoder IS
+    signal lsig_rTypeSub : std_ulogic;
+BEGIN
+    lsig_rTypeSub <= funct7 and op; -- true for R-type substract
+
+    decode : process(op, funct3, funct7, ALUOp, lsig_rTypeSub)
+    begin
+        case ALUOp is
+            when "00" => ALUControl <= "000" after g_tDec; -- addition
+            when "01" => ALUControl <= "001" after g_tDec; -- substraction
+            when others =>
+                case funct3 is -- R-type or I-type
+                    when "000" =>
+                        if lsig_rTypeSub = '1' then
+                            ALUControl <= "001" after g_tDec; -- sub
+                        else
+                            ALUControl <= "000" after g_tDec; -- add, addi
+                        end if;
+                    when "010" => ALUControl <= "101" after g_tDec; -- slt, slti
+                    when "110" => ALUControl <= "011" after g_tDec; -- or, ori
+                    when "111" => ALUControl <= "010" after g_tDec; -- and, andi
+                    when others => ALUControl <= "---" after g_tDec; -- unknown
+                end case;
+        end case;
+    end process decode;
+END ARCHITECTURE rtl;

Libs/RiscV/HEIRV32/hdl/bramAddrReducer_rtl.vhd

@@ -0,0 +1,6 @@
+
+ARCHITECTURE rtl OF bramAddrReducer IS
+BEGIN
+	-- +2 to srr(2) the address (as it makes +4)
+	addrOut <= std_ulogic_vector(addrIn(addrOut'high+2 downto addrOut'low+2));
+END ARCHITECTURE rtl;

Libs/RiscV/HEIRV32/hdl/bufferStdULogEnable_rtl.vhd

@@ -0,0 +1,17 @@
+
+ARCHITECTURE rtl OF bufferStdULogEnable IS
+BEGIN
+
+    buffering:process(rst, CLK)
+	begin
+		if rst = '1' then
+			out1 <= (others=>'0');
+		elsif rising_edge(CLK) then
+			if EN = '1' then
+				out1 <= in1;
+			end if;
+		end if;
+	end process buffering;
+	
+END ARCHITECTURE rtl;
+

Libs/RiscV/HEIRV32/hdl/bufferUnsignedEnable_rtl.vhd

@@ -0,0 +1,16 @@
+
+ARCHITECTURE rtl OF bufferUnsignedEnable IS
+BEGIN
+
+    buffering:process(rst, CLK)
+	begin
+		if rst = '1' then
+			out1 <= (others=>'0') after g_tPC;
+		elsif rising_edge(CLK) then
+			if EN = '1' then
+				out1 <= in1 after g_tPC;
+			end if;
+		end if;
+	end process buffering;
+
+END ARCHITECTURE rtl;

Libs/RiscV/HEIRV32/hdl/extend_rtl.vhd

@@ -0,0 +1,26 @@
+
+ARCHITECTURE rtl OF extend IS
+BEGIN
+
+    extend : process(input, src)
+    begin
+        case src is
+            when "00" => -- I-type
+                extended <= (12 to 31 => input(31)) &
+                    input(31 downto 20) after g_tExt;
+            when "01" => -- S-types (stores)
+                extended <= (12 to 31 => input(31)) &
+                    input(31 downto 25) & input(11 downto 7) after g_tExt;
+            when "10" => -- B-type (branches)
+                extended <= (12 to 31 => input(31)) & input(7) &
+                    input(30 downto 25) & input(11 downto 8) & '0' after g_tExt;
+            when "11" => -- J-type (jal)
+                extended <= (20 to 31 => input(31)) &
+                    input(19 downto 12) & input(20) &
+                    input(30 downto 21) & '0' after g_tExt;
+            when others => -- impossible
+                extended <= (others => '-') after g_tExt;
+        end case;
+    end process extend;
+
+END ARCHITECTURE rtl;

Libs/RiscV/HEIRV32/hdl/mux4To1ULogVec_rtl.vhd

@@ -0,0 +1,16 @@
+
+ARCHITECTURE rtl OF mux4To1ULogVec IS
+BEGIN
+
+  muxSelect: process(sel, in1, in2, in3, in4)
+  begin
+    case to_integer(unsigned(sel)) is
+      when 0 => out1 <= in1 after g_tMux;
+      when 1 => out1 <= in2 after g_tMux;
+      when 2 => out1 <= in3 after g_tMux;
+      when 3 => out1 <= in4 after g_tMux;
+      when others => out1 <= (others => 'X') after g_tMux;
+    end case;
+  end process muxSelect;
+
+END ARCHITECTURE rtl;

Libs/RiscV/HEIRV32/hdl/registerFile_rtl.vhd

@@ -0,0 +1,53 @@
+
+ARCHITECTURE rtl OF registerFile IS
+    -- Bank of register
+    type t_registersBank is array (31 downto 0) of
+        std_ulogic_vector(31 downto 0);
+    -- A bank of registers
+    signal larr_registers: t_registersBank;
+    signal lvec_btns : std_ulogic_vector(31 downto 0);
+BEGIN
+    -- Special regs
+    process(rst, clk)
+    begin
+        if rst = '1' then
+            lvec_btns <= (others => '0');
+        elsif rising_edge(clk) then
+            lvec_btns <= (btns'length to g_datawidth-1 => '0') & btns;
+        end if;
+    end process;
+
+    -- Clocked write
+    process(rst, clk) begin
+    if rst = '1' then
+        larr_registers <= (others => (others => '0')) after g_tRfWr;
+    elsif rising_edge(clk) then
+        if writeEnable3 = '1' and en = '1' then
+            larr_registers(to_integer(unsigned(addr3))) <= writeData after (g_tRfWr + g_tSetup);
+        end if;
+    end if;
+    end process;
+
+    -- Comb. read
+    -- Addr 0 wired to 0s
+    process(addr1, addr2) begin
+        if (to_integer(unsigned(addr1)) = 0) then
+            RD1 <= (others => '0') after g_tRfRd;
+        elsif (to_integer(unsigned(addr1)) = 31) then -- buttons
+            RD1 <= lvec_btns after g_tRfRd;
+        else
+            RD1 <= larr_registers(to_integer(unsigned(addr1))) after g_tRfRd;
+        end if;
+
+        if (to_integer(unsigned(addr2)) = 0) then
+            RD2 <= (others => '0') after g_tRfRd;
+        elsif (to_integer(unsigned(addr2)) = 31) then -- buttons
+            RD2 <= lvec_btns after g_tRfRd;
+        else
+            RD2 <= larr_registers(to_integer(unsigned(addr2))) after g_tRfRd;
+        end if;
+    end process;
+
+    leds <= larr_registers(30);
+
+END ARCHITECTURE rtl;

Libs/RiscV/HEIRV32/hds/.hdlsidedata/_ALU_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/hds/.hdlsidedata/_aluDecoder_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/hds/.hdlsidedata/_bramAddrReducer_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/hds/.hdlsidedata/_bufferStdULogEnable_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/hds/.hdlsidedata/_bufferUnsignedEnable_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/hds/.hdlsidedata/_extend_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/hds/.hdlsidedata/_instrDecoder_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/hds/.hdlsidedata/_instructionForwarder_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/hds/.hdlsidedata/_mainfsm_fsm.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/RiscV/HEIRV32/hds/.hdlsidedata/_mux4To1ULogVec_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/hds/.hdlsidedata/_registerFile_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32/hds/_alu._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom ALU_rtl.vhd

Libs/RiscV/HEIRV32/hds/_aludecoder._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom aluDecoder_rtl.vhd

Libs/RiscV/HEIRV32/hds/_bramaddrreducer._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom bramAddrReducer_rtl.vhd

Libs/RiscV/HEIRV32/hds/_bufferstdulogenable._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom bufferStdULogEnable_rtl.vhd

Libs/RiscV/HEIRV32/hds/_bufferunsignedenable._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom bufferUnsignedEnable_rtl.vhd

Libs/RiscV/HEIRV32/hds/_extend._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom extend_rtl.vhd

Libs/RiscV/HEIRV32/hds/_mux4to1ulogvec._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom mux4To1ULogVec_rtl.vhd

Libs/RiscV/HEIRV32/hds/_registerfile._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom registerFile_rtl.vhd

Libs/RiscV/HEIRV32_test/hdl/heirv32_mc_tester_test.vhd

@@ -0,0 +1,118 @@
+LIBRARY std;
+  USE std.textio.ALL;
+
+LIBRARY ieee;
+  USE ieee.std_logic_textio.ALL;
+
+LIBRARY Common_test;
+  USE Common_test.testutils.all;
+
+ARCHITECTURE test OF heirv32_mc_tester IS
+
+  constant clockPeriod  : time := 1.0/66E6 * 1 sec;
+  signal sClock         : std_uLogic := '1';
+  signal sReset         : std_uLogic ;
+
+  signal testInfo       : string(1 to 40) := (others => ' ');
+
+BEGIN
+
+ ------------------------------------------------------------------------------
+                                                              -- reset and clock
+  sReset <= '1', '0' after 3.5*clockPeriod;
+  rst <= sReset;
+
+  sClock <= not sClock after clockPeriod/2;
+  clk <= transport sClock after 0.9*clockPeriod;
+
+  btns <= (others => '0');
+
+  process
+    -- Wait list
+    -- 3 clk for beq
+    -- 4 clk for others
+    -- 5 clk for lw
+  begin
+    en <= '0';
+
+    testInfo <= pad("Wait reset", testInfo'length);
+    wait until rst = '0';
+
+    while true loop
+      en <= '1';
+
+      testInfo <= pad("Addi, addr. 00", testInfo'length);
+      wait until clk'event and clk = '1';
+      wait for 3*clockPeriod;
+
+      testInfo <= pad("Addi, addr. 04", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Addi, addr. 08", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Or, addr. 0C", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("And, addr. 10", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Add, addr. 14", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Beq, addr. 18", testInfo'length);
+      wait for 3*clockPeriod;
+
+      testInfo <= pad("Slt, addr. 1C", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Beq, addr. 20", testInfo'length);
+      wait for 3*clockPeriod;
+
+      --testInfo <= pad("Addi, addr. 24", testInfo'length);
+      --wait for 4*clockPeriod;
+
+      testInfo <= pad("Slt, addr. 28", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Add, addr. 2C", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Sub, addr. 30", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Sw, addr. 34", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Lw, addr. 38", testInfo'length);
+      wait for 5*clockPeriod;
+
+      testInfo <= pad("Add, addr. 3C", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Jal, addr. 40", testInfo'length);
+      wait for 4*clockPeriod;
+
+      --testInfo <= pad("Addi, addr. 44", testInfo'length);
+      --wait for 4*clockPeriod;
+
+      testInfo <= pad("Add, addr. 48", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Sw, addr.4C", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Beq, addr. 50", testInfo'length);
+      wait for 2.8*clockPeriod;
+
+      en <= '0';
+      testInfo <= pad("Wait a bit, program should restart", testInfo'length);
+      wait for 9.2*clockPeriod;
+      testInfo <= pad("PC should go to 0 on clock", testInfo'length);
+      en <= '1';
+      wait until clk'event and clk = '1';
+
+    end loop;
+  end process;
+
+END ARCHITECTURE test;

Libs/RiscV/HEIRV32_test/hdl/heirv32_sc_tester_rtl.vhd

@@ -0,0 +1,116 @@
+LIBRARY std;
+  USE std.textio.ALL;
+
+LIBRARY ieee;
+  USE ieee.std_logic_textio.ALL;
+
+LIBRARY Common_test;
+  USE Common_test.testutils.all;
+
+ARCHITECTURE rtl OF heirv32_sc_tester IS
+
+  constant clockPeriod  : time := 1.0/66E6 * 1 sec;
+  signal sClock         : std_uLogic := '1';
+  signal sReset         : std_uLogic ;
+
+  signal testInfo       : string(1 to 40) := (others => ' ');
+
+BEGIN
+
+ ------------------------------------------------------------------------------
+                                                              -- reset and clock
+  sReset <= '1', '0' after 3.5*clockPeriod;
+  rst <= sReset;
+
+  sClock <= not sClock after clockPeriod/2;
+  clk <= transport sClock after 0.9*clockPeriod;
+
+  btns <= (others => '0');
+
+  process
+    -- Wait list
+    -- 1 for all
+  begin
+    en <= '0';
+
+    testInfo <= pad("Wait reset", testInfo'length);
+    wait until rst = '0';
+
+    while true loop
+      en <= '1';
+
+      testInfo <= pad("Addi, addr. 00", testInfo'length);
+      wait until clk'event and clk = '1';
+      wait for clockPeriod;
+
+      testInfo <= pad("Addi, addr. 04", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Addi, addr. 08", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Or, addr. 0C", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("And, addr. 10", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Add, addr. 14", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Beq, addr. 18", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Slt, addr. 1C", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Beq, addr. 20", testInfo'length);
+      wait for clockPeriod;
+
+      --testInfo <= pad("Addi, addr. 24", testInfo'length);
+      --wait for clockPeriod;
+
+      testInfo <= pad("Slt, addr. 28", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Add, addr. 2C", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Sub, addr. 30", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Sw, addr. 34", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Lw, addr. 38", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Add, addr. 3C", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Jal, addr. 40", testInfo'length);
+      wait for clockPeriod;
+
+      --testInfo <= pad("Addi, addr. 44", testInfo'length);
+      --wait for clockPeriod;
+
+      testInfo <= pad("Add, addr. 48", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Sw, addr.4C", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Beq, addr. 50", testInfo'length);
+      wait for 0.8*clockPeriod;
+
+      en <= '0';
+      testInfo <= pad("Wait a bit, PC should be 0", testInfo'length);
+      wait for 9.2*clockPeriod;
+      testInfo <= pad("Enabling system", testInfo'length);
+      en <= '1';
+      wait until clk'event and clk = '1';
+
+    end loop;
+  end process;
+
+END ARCHITECTURE rtl;

Libs/RiscV/HEIRV32_test/hdl/universalTester_test.vhd

@@ -0,0 +1,51 @@
+LIBRARY std;
+  USE std.textio.ALL;
+
+LIBRARY ieee;
+  USE ieee.std_logic_textio.ALL;
+
+LIBRARY Common_test;
+  USE Common_test.testutils.all;
+
+ARCHITECTURE test OF universalTester IS
+
+  constant clockPeriod  : time := 1.0/66E6 * 1 sec;
+  signal sClock         : std_uLogic := '1';
+  signal sReset         : std_uLogic ;
+
+  signal testInfo       : string(1 to 40) := (others => ' ');
+
+BEGIN
+
+ ------------------------------------------------------------------------------
+                                                              -- reset and clock
+  sReset <= '1', '0' after 3.5*clockPeriod;
+  rst <= sReset;
+
+  sClock <= not sClock after clockPeriod/2;
+  clk <= transport sClock after 0.9*clockPeriod;
+
+  btns <= (others => '1'), (others=>'0') after 4.15 us;
+
+  process
+    -- Wait list
+    -- 3 clk for beq
+    -- 4 clk for others
+    -- 5 clk for lw
+  begin
+    en <= '0';
+
+    testInfo <= pad("Wait reset", testInfo'length);
+    wait until rst = '0';
+
+    while true loop
+      en <= '1';
+
+      testInfo <= pad("Running", testInfo'length);
+      wait;
+
+    end loop;
+  end process;
+
+END ARCHITECTURE test;
+

Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_mc_tester_test.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_sc_tester_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_sc_tester_test.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_93

Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_tb_universal.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_tester_test.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_universalTester_test.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32_test/hds/_heirv32_mc_tb._epf

@@ -0,0 +1,3 @@
+DEFAULT_FILE atom heirv32_mc_tb/struct.bd
+DEFAULT_ARCHITECTURE atom struct
+TOP_MARKER atom 1

Libs/RiscV/HEIRV32_test/hds/_heirv32_mc_tester._epf

@@ -0,0 +1,2 @@
+DEFAULT_FILE atom heirv32_mc_tester_test.vhd
+DEFAULT_ARCHITECTURE atom test

Libs/RiscV/HEIRV32_test/hds/_heirv32_sc_tb._epf

@@ -0,0 +1,3 @@
+DEFAULT_ARCHITECTURE atom struct
+DEFAULT_FILE atom heirv32_sc_tb/struct.bd
+TOP_MARKER atom 1

Libs/RiscV/HEIRV32_test/hds/_heirv32_sc_tester._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom heirv32_sc_tester_rtl.vhd

Libs/RiscV/HEIRV32_test/hds/_universaltester._epf

@@ -0,0 +1,2 @@
+DEFAULT_FILE atom universalTester_test.vhd
+DEFAULT_ARCHITECTURE atom test