26 Commits

Author SHA1 Message Date
693676d61a Merge pull request 'feature: add IEC gates' (#11) from bono/circuiteria:add_iec_gates into dev
Reviewed-on: #11
Reviewed-by: Louis Heredero <louis@herdac.ch>
2025-06-29 13:19:56 +00:00
94d5d6b854 add examples and add iec gates to manual 2025-06-28 13:56:22 -03:00
71f128f6c9 fix typo in xnor gate 2025-06-28 13:55:14 -03:00
ea8277ee5b rename iec gates to have consistent naming 2025-06-28 12:28:28 -03:00
c5e4f8039a improve iec-gate 2025-06-28 12:10:00 -03:00
8c91ccdd54 improve default-draw-shape by drawing a rectangle 2025-06-28 11:40:36 -03:00
9966656e8b add examples 2025-06-22 14:49:11 -03:00
3ccb79c6c2 add iec gates 2025-06-22 14:46:52 -03:00
2bb7e3b5a9 Merge pull request 'v0.2.0: Updates' (#5) from dev into main
Reviewed-on: #5
2025-03-01 21:28:24 +00:00
371caf094c updated README and manual with new version 2025-03-01 22:23:52 +01:00
841f53e76c Merge pull request 'updated compiler version + dependencies' (#4) from feat/updates-1 into dev
Reviewed-on: #4
2025-03-01 21:17:27 +00:00
ff0b91e683 updated compiler version + dependencies 2025-03-01 21:22:08 +01:00
e1e561bb6c fixed y-alignment for north/south ports 2024-11-09 23:03:03 +01:00
9a1fda087c prepared for publication + bumped to 0.1.0 2024-10-02 21:09:48 +02:00
c5a0cf7ecc fixed typo in default param value 2024-10-02 21:04:40 +02:00
9a6973fb89 fixed README links 2024-05-18 23:55:06 +02:00
d8094384ad added examples to README.md 2024-05-18 23:50:29 +02:00
86ca91920f added gallery/platypus 2024-05-18 23:46:29 +02:00
64d6635d5f added gallery/test6 2024-05-18 22:36:38 +02:00
6a6ae96a96 changed AND design (circle arc instead of bezier) 2024-05-18 22:36:27 +02:00
a856b7f634 added doc for wire.intersection 2024-05-18 21:52:46 +02:00
011802ffbe fixed minor issues + changed some default styles 2024-05-18 21:45:12 +02:00
4fae4fe19a fixed gates y alignment 2024-05-18 18:27:57 +02:00
d6248865b3 added gallery rendering script 2024-05-18 18:08:36 +02:00
2317fec71d fixed wire name rotation 2024-05-18 18:08:22 +02:00
ff9ad9e94a changed version number 2024-05-18 17:08:08 +02:00
53 changed files with 1047 additions and 116 deletions

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@ -1,3 +1,64 @@
# circuiteria
Drawing block circuits with Typst made easy, using CeTZ
Circuiteria is a [Typst](https://typst.app) package for drawing block circuit diagrams using the [CeTZ](https://typst.app/universe/package/cetz) package.
<p align="center">
<img src="./gallery/platypus.png" alt="Perry the platypus">
</p>
## Examples
<table>
<tr>
<td colspan="2">
<a href="./gallery/test.typ">
<img src="./gallery/test.png" width="500px">
</a>
</td>
</tr>
<tr>
<td colspan="2">A bit of eveything</td>
</tr>
<tr>
<td colspan="2">
<a href="./gallery/test5.typ">
<img src="./gallery/test5.png" width="500px">
</a>
</td>
</tr>
<tr>
<td colspan="2">Wires everywhere</td>
</tr>
<tr>
<td>
<a href="./gallery/test4.typ">
<img src="./gallery/test4.png" width="250px">
</a>
</td>
<td>
<a href="./gallery/test6.typ">
<img src="./gallery/test6.png" width="250px">
</a>
</td>
</tr>
<tr>
<td>Groups</td>
<td>Rotated</td>
</tr>
</table>
> **Note**\
> These circuit layouts were copied from a digital design course given by prof. S. Zahno and recreated using this package
*Click on the example image to jump to the code.*
## Usage
For more information, see the [manual](manual.pdf)
To use this package, simply import [circuiteria](https://typst.app/universe/package/circuiteria) and call the `circuit` function:
```typ
#import "@preview/circuiteria:0.2.0"
#circuiteria.circuit({
import circuiteria: *
...
})
```

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@ -1,4 +1,4 @@
#import "@preview/cetz:0.2.2": draw
#import "@preview/cetz:0.3.2": draw
#import "../src/circuit.typ": circuit
#import "../src/util.typ"

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@ -115,6 +115,46 @@ gates.gate-xnor(x: 0, y: 0, w: 1.5, h: 1.5)
gates.gate-xnor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
```, vertical: true)
#let iec-gate-and = example(```
gates.iec-gate-and(x: 0, y: 0, w: 1.5, h: 1.5)
gates.iec-gate-and(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
```, vertical: true)
#let iec-gate-nand = example(```
gates.iec-gate-nand(x: 0, y: 0, w: 1.5, h: 1.5)
gates.iec-gate-nand(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
```, vertical: true)
#let iec-gate-or = example(```
gates.iec-gate-or(x: 0, y: 0, w: 1.5, h: 1.5)
gates.iec-gate-or(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
```, vertical: true)
#let iec-gate-nor = example(```
gates.iec-gate-nor(x: 0, y: 0, w: 1.5, h: 1.5)
gates.iec-gate-nor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
```, vertical: true)
#let iec-gate-xor = example(```
gates.iec-gate-xor(x: 0, y: 0, w: 1.5, h: 1.5)
gates.iec-gate-xor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
```, vertical: true)
#let iec-gate-xnor = example(```
gates.iec-gate-xnor(x: 0, y: 0, w: 1.5, h: 1.5)
gates.iec-gate-xnor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
```, vertical: true)
#let iec-gate-buf = example(```
gates.iec-gate-buf(x: 0, y: 0, w: 1.5, h: 1.5)
gates.iec-gate-buf(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
```, vertical: true)
#let iec-gate-not = example(```
gates.iec-gate-not(x: 0, y: 0, w: 1.5, h: 1.5)
gates.iec-gate-not(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
```, vertical: true)
#let group = example(```
element.group(
id: "g1", name: "Group 1", stroke: (dash: "dashed"),
@ -140,4 +180,11 @@ element.block(id: "b3", w: 2, h: 3,
wire.wire("w1", ("b1-port-out", "b3-port-in1"))
wire.wire("w2", ("b2-port-out", "b3-port-in2"),
style: "zigzag")
```)
#let intersection = example(```
wire.wire("w1", ((0, 0), (1, 1)), style: "zigzag")
wire.wire("w2", ((0, 0), (1, -.5)),
style: "zigzag", zigzag-ratio: 80%)
wire.intersection("w1.zig")
```)

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#import "../src/lib.typ": *
#set page(width: auto, height: auto, margin: .5cm)
#let teal = rgb(37, 155, 166)
#let orange = rgb(254, 160, 93)
#let brown = rgb(97, 54, 60)
#circuit({
element.group(id: "platypus", name: "A platypus", {
element.block(
x: 0, y: 0, w: 2, h: 3, id: "body",
fill: teal,
ports: (
east: (
(id: "out"),
)
),
ports-margins: (
east: (50%, 10%)
)
)
element.block(
x: 2.5, y: 1.5, w: 1.5, h: 1, id: "beak",
fill: orange,
ports: (
south: (
(id: "in"),
)
)
)
wire.wire("w1", ("body-port-out", "beak-port-in"), style: "zigzag", zigzag-ratio: 100%)
})
let O = (rel: (2, 0), to: "platypus.south-east")
element.group(id: "perry", name: "Perry the platypus", {
element.block(
x: (rel: 0, to: O), y: 0, w: 2, h: 3, id: "body",
fill: teal,
ports: (
east: (
(id: "out"),
)
),
ports-margins: (
east: (50%, 10%)
)
)
element.block(
x: (rel: 2.5, to: O), y: 1.5, w: 1.5, h: 1, id: "beak",
fill: orange,
ports: (
south: (
(id: "in"),
)
)
)
element.block(
x: (rel: 0.25, to: O), y: 3.2, w: 1.5, h: 0.5, id: "hat",
fill: brown
)
wire.wire("w2", ("body-port-out", "beak-port-in"), style: "zigzag", zigzag-ratio: 100%)
})
wire.wire(
"w3",
("platypus.east", (horizontal: "perry.west", vertical: ())),
directed: true,
bus: true
)
})

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#import "../src/lib.typ": circuit, element, util, wire
#set page(flipped: true)
#set page(width: auto, height: auto, margin: .5cm)
#circuit({
element.block(
@ -294,6 +294,6 @@
bus: true
)
wire.intersection("wResMP-RegFile.dodge-end")
wire.intersection("wResMP-AdrSrc.dodge-end")
wire.intersection("wResMP-RegFile.dodge-end", radius: .2)
wire.intersection("wResMP-AdrSrc.dodge-end", radius: .2)
})

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#import "../src/lib.typ": circuit, element, util, wire
#set page(flipped: true)
#set page(width: auto, height: auto, margin: .5cm)
#circuit({
element.block(
@ -307,6 +307,6 @@
bus: true
)
wire.intersection("wResMP-RegFile.dodge-end")
wire.intersection("wResMP-AdrSrc.dodge-end")
wire.intersection("wResMP-RegFile.dodge-end", radius: .2)
wire.intersection("wResMP-AdrSrc.dodge-end", radius: .2)
})

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#import "@preview/cetz:0.2.2": draw
#import "@preview/cetz:0.3.2": draw
#import "../src/lib.typ": circuit, element, util, wire
#set page(flipped: true)
#let debug = false
#set page(width: auto, height: auto, margin: .5cm)
#circuit({
element.block(
@ -14,18 +13,14 @@
(id: "out1"),
(id: "out2"),
)
),
debug: (
ports: debug
)
)
element.gate-and(
x: 4, y: 0, w: 2, h: 2, id: "and1", debug: (ports: debug),
x: 4, y: 0, w: 2, h: 2, id: "and1",
inverted: ("in1")
)
element.gate-or(
x: 7, y: 0, w: 2, h: 2, id: "or1", debug: (ports: debug),
x: 7, y: 0, w: 2, h: 2, id: "or1",
inverted: ("in0", "out")
)
@ -47,7 +42,7 @@
)
element.gate-and(
x: 11, y: 0, w: 2, h: 2, id: "and2", inputs: 3, debug: (ports: debug),
x: 11, y: 0, w: 2, h: 2, id: "and2", inputs: 3,
inverted: ("in0", "in2")
)
for i in range(3) {
@ -55,35 +50,35 @@
}
element.gate-xor(
x: 14, y: 0, w: 2, h: 2, id: "xor", debug: (ports: debug),
x: 14, y: 0, w: 2, h: 2, id: "xor",
inverted: ("in1")
)
element.gate-buf(
x: 0, y: -3, w: 2, h: 2, id: "buf", debug: (ports: debug)
x: 0, y: -3, w: 2, h: 2, id: "buf"
)
element.gate-not(
x: 0, y: -6, w: 2, h: 2, id: "not", debug: (ports: debug)
x: 0, y: -6, w: 2, h: 2, id: "not"
)
element.gate-and(
x: 3, y: -3, w: 2, h: 2, id: "and", debug: (ports: debug)
x: 3, y: -3, w: 2, h: 2, id: "and"
)
element.gate-nand(
x: 3, y: -6, w: 2, h: 2, id: "nand", debug: (ports: debug)
x: 3, y: -6, w: 2, h: 2, id: "nand"
)
element.gate-or(
x: 6, y: -3, w: 2, h: 2, id: "or", debug: (ports: debug)
x: 6, y: -3, w: 2, h: 2, id: "or"
)
element.gate-nor(
x: 6, y: -6, w: 2, h: 2, id: "nor", debug: (ports: debug)
x: 6, y: -6, w: 2, h: 2, id: "nor"
)
element.gate-xor(
x: 9, y: -3, w: 2, h: 2, id: "xor", debug: (ports: debug)
x: 9, y: -3, w: 2, h: 2, id: "xor"
)
element.gate-xnor(
x: 9, y: -6, w: 2, h: 2, id: "xnor", debug: (ports: debug)
x: 9, y: -6, w: 2, h: 2, id: "xnor"
)
})

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#import "@preview/cetz:0.2.2": draw
#import "@preview/cetz:0.3.2": draw
#import "../src/lib.typ": *
#set page(flipped: true)
#set page(width: auto, height: auto, margin: .5cm)
#circuit({
element.group(id: "toplvl", name: "Toplevel", {
@ -18,7 +18,7 @@
name: "Datapath",
ports: (
north: (
(id: "clk", clock: true),
(id: "clk", clock: true, small: true),
(id: "Zero"),
(id: "Regsrc"),
(id: "PCSrc"),
@ -104,7 +104,7 @@
name: "Data\n Memory",
ports: (
north: (
(id: "clk", clock: true),
(id: "clk", clock: true, small: true),
(id: "WE", name: "WE")
),
west: (
@ -200,18 +200,22 @@
draw.content("dmem.south-west", [*External Memories*], anchor: "north", padding: 10pt)
})
wire.wire(
"w-dp-clk",
("dp-port-clk", (-1, 4.2)),
style: "zigzag",
zigzag-dir: "horizontal",
zigzag-ratio: 100%
draw.line(name: "w-dp-clk",
"dp-port-clk",
(rel: (0, .5), to: ()),
(
rel: (-.5, 0),
to: (horizontal: "toplvl.west", vertical: ())
)
)
draw.content("w-dp-clk.end", "clk", anchor: "east", padding: 3pt)
wire.wire(
"w-dp-rst",
("dp-port-rst", (horizontal: (-1, 0), vertical: ()))
draw.line(name: "w-dp-rst",
"dp-port-rst",
(
rel: (-.5, 0),
to: (horizontal: "toplvl.west", vertical: ())
)
)
draw.content("w-dp-rst.end", "rst", anchor: "east", padding: 3pt)
})

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#import "@preview/cetz:0.2.2": draw
#import "@preview/cetz:0.3.2": draw
#import "../src/lib.typ": *
#set page(flipped: true, paper: "a3")
#set page(width: auto, height: auto, margin: .5cm)
#circuit({
element.multiplexer(
@ -202,8 +202,8 @@
style: "zigzag",
zigzag-ratio: 1
)
wire.intersection("wPC2.zig", radius: 2pt)
wire.intersection("wPC2.zag", radius: 2pt)
wire.intersection("wPC2.zig")
wire.intersection("wPC2.zag")
wire.stub("PCAdd-port-in2", "west", name: "4", length: 1.5)
wire.wire(
"wPC+4", ("PCAdd-port-out", "PCMux-port-in0"),
@ -278,11 +278,11 @@
reverse: true,
slice: (31, 7)
)
wire.intersection("wF3.end", radius: 2pt)
wire.intersection("wF7.end", radius: 2pt)
wire.intersection("wA1.end", radius: 2pt)
wire.intersection("wA2.end", radius: 2pt)
wire.intersection("wA3.end", radius: 2pt)
wire.intersection("wF3.end")
wire.intersection("wF7.end")
wire.intersection("wA1.end")
wire.intersection("wA2.end")
wire.intersection("wA3.end")
wire.stub("RegFile-port-clk", "north", name: "clk", length: 0.25)
wire.wire("wRD2", ("RegFile-port-RD2", "SrcBMux-port-in0"))
@ -293,7 +293,7 @@
name: "WriteData",
name-pos: "end"
)
wire.intersection("wWD.zig", radius: 2pt)
wire.intersection("wWD.zig")
wire.wire(
"wImmALU", ("Ext-port-out", "SrcBMux-port-in1"),
@ -305,7 +305,7 @@
wire.wire(
"wImmJump", ("Ext-port-out", "JumpAdd-port-in2")
)
wire.intersection("wImmALU.zig", radius: 2pt)
wire.intersection("wImmALU.zig")
wire.wire(
"wJumpPC", ("JumpAdd-port-out", "PCMux-port-in1"),
style: "dodge",
@ -351,7 +351,7 @@
dodge-y: 2,
dodge-margins: (3, 2)
)
wire.intersection("wALURes2.start2", radius: 2pt)
wire.intersection("wALURes2.start2")
wire.stub("DMem-port-clk", "north", name: "clk", length: 0.25)
wire.wire(

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#import "@preview/cetz:0.3.2": draw, vector
#import "../src/lib.typ": *
#set page(width: auto, height: auto, margin: .5cm)
#circuit({
element.multiplexer(
x: 10, y: 0, w: 1, h: 6, id: "ResMux",
entries: ("000", "001", "010", "011", "101"),
h-ratio: 90%,
fill: util.colors.blue
)
element.extender(
x: (rel: -3, to: "ResMux.west"),
y: (from: "ResMux-port-in4", to: "out"),
w: 2, h: 1, id: "Ext",
name: "Zero Ext",
name-anchor: "south",
fill: util.colors.green
)
gates.gate-or(
x: (rel: -2, to: "ResMux.west"),
y: (from: "ResMux-port-in3", to: "out"),
w: 1, h: 1, id: "Or"
)
gates.gate-and(
x: (rel: -2, to: "ResMux.west"),
y: (from: "ResMux-port-in2", to: "out"),
w: 1, h: 1, id: "And"
)
element.alu(
x: (rel: -2.5, to: "Ext.west"),
y: (from: "ResMux-port-in0", to: "out"),
w: 1.5, h: 3, id: "Add",
name: text("+", size: 1.5em),
name-anchor: "name",
fill: util.colors.pink
)
element.multiplexer(
x: (rel: -1.5, to: "Add.west"),
y: (from: "Add-port-in1", to: "out"),
w: 0.5, h: 1.5, id: "NotMux",
h-ratio: 80%,
fill: util.colors.blue
)
gates.gate-not(
x: (rel: -2, to: "NotMux.west"),
y: (from: "NotMux-port-in1", to: "out"),
w: 1, h: 1, id: "Not"
)
draw.hide(
draw.line(name: "l1",
"Not-port-in0",
(rel: (-2, 0), to: ()),
(horizontal: (), vertical: "NotMux-port-in0")
)
)
let b = "l1.end"
draw.hide(
draw.line(name: "l2",
b,
(horizontal: (), vertical: "Add-port-in2")
)
)
let a = "l2.end"
wire.wire("wB0", (b, "NotMux-port-in0"), bus: true)
wire.wire(
"wB1", (b, "Not-port-in0"),
style: "zigzag",
zigzag-ratio: 1.5,
bus: true
)
wire.wire(
"wB2", (b, "And-port-in0"),
style: "zigzag",
zigzag-ratio: 1,
bus: true
)
wire.wire(
"wB3", (b, "Or-port-in0"),
style: "zigzag",
zigzag-ratio: 1,
bus: true
)
wire.intersection("wB1.zig")
wire.intersection("wB2.zig")
wire.intersection("wB2.zag")
wire.wire("wNot", ("Not-port-out", "NotMux-port-in1"), bus: true)
wire.wire("wAddA", ("NotMux-port-out", "Add-port-in1"), bus: true)
wire.wire("wA0", (a, "Add-port-in2"), bus: true)
wire.wire(
"wA1", (a, "And-port-in1"),
style: "zigzag",
zigzag-ratio: 0.5,
bus: true
)
wire.wire(
"wA2", (a, "Or-port-in1"),
style: "zigzag",
zigzag-ratio: 0.5,
bus: true
)
wire.intersection("wA1.zig")
wire.intersection("wA1.zag")
wire.wire("wMux0", ("Add-port-out", "ResMux-port-in0"), bus: true)
wire.wire(
"wMux1", ("Add-port-out", "ResMux-port-in1"),
style: "zigzag",
zigzag-ratio: 2,
bus: true
)
wire.wire("wMux2", ("And-port-out", "ResMux-port-in2"), bus: true)
wire.wire("wMux3", ("Or-port-out", "ResMux-port-in3"), bus: true)
wire.wire("wMux4", ("Ext-port-out", "ResMux-port-in4"), bus: true)
wire.wire(
"wAdd", ("Add-port-out", "Ext-port-in"),
style: "zigzag",
zigzag-ratio: 0.5,
bus: true
)
wire.intersection("wMux1.zig")
wire.intersection("wAdd.zig")
let c = (rel: (0, 2), to: "ResMux.north")
wire.wire("wResCtrl", (c, "ResMux.north"), bus: true)
wire.wire(
"wAddCtrl", (c, "Add.north"),
style: "zigzag",
zigzag-dir: "horizontal"
)
let d = (rel: (1, 0), to: "ResMux-port-out")
wire.wire("wRes", ("ResMux-port-out", d), bus: true)
draw.content(
"wAddCtrl.zag",
[ALUControl#sub("[1]")],
anchor: "south-west",
padding: 3pt
)
wire.wire(
"wCout", ("Add.south", (horizontal: (), vertical: "Ext.north-east"))
)
draw.content(
"wCout.end",
[C#sub("out")],
angle: 90deg,
anchor: "east",
padding: 3pt
)
draw.content(
a,
[A],
angle: 90deg,
anchor: "south",
padding: 3pt
)
draw.content(
b,
[B],
angle: 90deg,
anchor: "south",
padding: 3pt
)
draw.content(
c,
[ALUControl#sub("[2:0]")],
angle: 90deg,
anchor: "west",
padding: 3pt
)
draw.content(
d,
[Result],
angle: 90deg,
anchor: "north",
padding: 3pt
)
draw.content(
("wAdd.zig", 0.2, "wAdd.zag"),
text("[N-1]", size: 0.8em),
angle: 90deg,
anchor: "north-east",
padding: 3pt
)
})

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98
gallery/test7.typ Normal file
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@ -0,0 +1,98 @@
#import "@preview/cetz:0.3.2": draw
#import "../src/lib.typ": circuit, element, util, wire
#set page(width: auto, height: auto, margin: .5cm)
#circuit({
element.iec-gate-buf(
x: 0,
y: 0,
w: 2,
h: 2,
id: "iec-buf",
inputs: 1,
)
wire.stub("iec-buf-port-in0", "west")
element.iec-gate-not(
x: 3,
y: 0,
w: 2,
h: 2,
id: "iec-not",
inputs: 1,
)
wire.stub("iec-not-port-in0", "west")
element.iec-gate-and(
id: "iec-and",
x: 0,
y: -3,
w: 2,
h: 2,
inputs: 2,
)
for i in range(2) {
wire.stub("iec-and-port-in" + str(i), "west")
}
element.iec-gate-nand(
id: "iec-nand",
x: 3,
y: -3,
w: 2,
h: 2,
inputs: 2,
)
for i in range(2) {
wire.stub("iec-nand-port-in" + str(i), "west")
}
element.iec-gate-or(
id: "iec-or",
x: 0,
y: -6,
w: 2,
h: 2,
inputs: 2,
)
for i in range(2) {
wire.stub("iec-or-port-in" + str(i), "west")
}
element.iec-gate-nor(
id: "iec-nor",
x: 3,
y: -6,
w: 2,
h: 2,
inputs: 2,
)
for i in range(2) {
wire.stub("iec-nor-port-in" + str(i), "west")
}
element.iec-gate-xor(
id: "iec-xor",
x: 0,
y: -9,
w: 2,
h: 2,
inputs: 2,
)
for i in range(2) {
wire.stub("iec-xor-port-in" + str(i), "west")
}
element.iec-gate-xnor(
id: "iec-nxor",
x: 3,
y: -9,
w: 2,
h: 2,
inputs: 2,
)
for i in range(2) {
wire.stub("iec-nxor-port-in" + str(i), "west")
}
})

11
justfile Normal file
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@ -0,0 +1,11 @@
# Local Variables:
# mode: makefile
# End:
gallery_dir := "./gallery"
set shell := ["bash", "-uc"]
manual:
typst c manual.typ manual.pdf
gallery:
for f in "{{gallery_dir}}"/*.typ; do typst c --root . "$f" "${f%typ}png"; done

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@ -1,5 +1,5 @@
#import "@preview/tidy:0.3.0"
#import "@preview/cetz:0.2.2": draw, canvas
#import "@preview/tidy:0.4.1"
#import "@preview/cetz:0.3.2": draw, canvas
#import "src/lib.typ"
#import "doc/examples.typ"
#import "src/circuit.typ": circuit
@ -12,7 +12,7 @@
numbering("1.1", ..num)
})
#{
outline(indent: true, depth: 3)
outline(indent: auto, depth: 3)
}
#show link: set text(blue)
@ -47,7 +47,7 @@
#set page(numbering: "1/1", header: align(right)[circuiteria #sym.dash.em v#lib.version])
#set page(
header: locate(loc => {
header: context {
let txt = [circuiteria #sym.dash.em v#lib.version]
let cnt = counter(heading)
let cnt-val = cnt.get()
@ -65,8 +65,8 @@
#rect(width: 100%, height: .5em, radius: .25em, stroke: none, fill: util.colors.values().at(i))
]
)
}),
footer: locate(loc => {
},
footer: context {
let cnt = counter(heading)
let cnt-val = cnt.get()
if cnt-val.len() < 2 { return }
@ -80,12 +80,12 @@
],
counter(page).display("1/1", both: true)
)
})
}
)
#let doc-ref(target, full: false, var: false) = {
let (module, func) = target.split(".")
let label-name = module + func
let label-name = module + "-" + func
let display-name = func
if full {
display-name = target
@ -94,7 +94,7 @@
label-name += "()"
display-name += "()"
}
link(label(label-name))[#display-name]
link(label(label-name), raw(display-name))
}
= Introduction
@ -103,11 +103,21 @@ This package provides a way to make beautiful block circuit diagrams using the C
= Usage
Simply import #link("src/lib.typ") and call the `circuit` function:
Simply import Circuiteria and call the `circuit` function:
#pad(left: 1em)[```typ
#import "src/lib.typ"
#lib.circuit({
import lib: *
#import "@preview/circuiteria:0.2.0"
#circuiteria.circuit({
import circuiteria: *
...
})
```]
== Project installation
If you have installed Circuiteria directly in your project, import #link("src/lib.typ") and call the `circuit` function:
#pad(left: 1em)[```typ
#import "src/lib.typ" as circuiteria
#circuiteria.circuit({
import circuiteria: *
...
})
```]
@ -117,6 +127,7 @@ Simply import #link("src/lib.typ") and call the `circuit` function:
#let circuit-docs = tidy.parse-module(
read("src/circuit.typ"),
name: "circuit",
old-syntax: true,
require-all-parameters: true
)
#tidy.show-module(circuit-docs)
@ -126,6 +137,7 @@ Simply import #link("src/lib.typ") and call the `circuit` function:
#let util-docs = tidy.parse-module(
read("src/util.typ"),
name: "util",
old-syntax: true,
require-all-parameters: true,
scope: (
util: util,
@ -140,6 +152,7 @@ Simply import #link("src/lib.typ") and call the `circuit` function:
#let wire-docs = tidy.parse-module(
read("src/wire.typ"),
name: "wire",
old-syntax: true,
require-all-parameters: true,
scope: (
wire: wire,
@ -161,6 +174,7 @@ Simply import #link("src/lib.typ") and call the `circuit` function:
read("src/elements/multiplexer.typ") + "\n" +
read("src/elements/group.typ"),
name: "element",
old-syntax: true,
scope: (
element: element,
circuit: circuit,
@ -181,8 +195,14 @@ Simply import #link("src/lib.typ") and call the `circuit` function:
read("src/elements/logic/and.typ") + "\n" +
read("src/elements/logic/buf.typ") + "\n" +
read("src/elements/logic/or.typ") + "\n" +
read("src/elements/logic/xor.typ"),
read("src/elements/logic/xor.typ") + "\n" +
read("src/elements/logic/iec_gate.typ") + "\n" +
read("src/elements/logic/iec_and.typ") + "\n" +
read("src/elements/logic/iec_buf.typ") + "\n" +
read("src/elements/logic/iec_or.typ") + "\n" +
read("src/elements/logic/iec_xor.typ"),
name: "gates",
old-syntax: true,
scope: (
element: element,
circuit: circuit,

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@ -1,4 +1,4 @@
#import "@preview/cetz:0.2.2": canvas
#import "@preview/cetz:0.3.2": canvas
#import "@preview/tidy:0.3.0"
/// Draws a block circuit diagram

View File

@ -11,5 +11,10 @@
#import "elements/logic/or.typ": gate-or, gate-nor
#import "elements/logic/xor.typ": gate-xor, gate-xnor
#import "elements/logic/buf.typ": gate-buf, gate-not
#import "elements/logic/iec_gate.typ": iec-gate
#import "elements/logic/iec_and.typ": iec-gate-and, iec-gate-nand
#import "elements/logic/iec_buf.typ": iec-gate-buf, iec-gate-not
#import "elements/logic/iec_or.typ": iec-gate-or, iec-gate-nor
#import "elements/logic/iec_xor.typ": iec-gate-xor, iec-gate-xnor
#import "elements/group.typ": group

View File

@ -1,4 +1,4 @@
#import "@preview/cetz:0.2.2": draw
#import "@preview/cetz:0.3.2": draw
#import "element.typ"
#import "ports.typ": add-port
@ -86,6 +86,7 @@
ports-y: (
in1: (h) => {h * 0.225},
in2: (h) => {h * 0.775},
out: (h) => {h * 0.5}
),
debug: debug
)

View File

@ -1,4 +1,4 @@
#import "@preview/cetz:0.2.2": draw
#import "@preview/cetz:0.3.2": draw
#import "element.typ"
#let draw-shape(id, tl, tr, br, bl, fill, stroke) = {

View File

@ -1,4 +1,4 @@
#import "@preview/cetz:0.2.2": draw, coordinate
#import "@preview/cetz:0.3.2": draw, coordinate
#import "ports.typ": add-ports, add-port
#import "../util.typ"
@ -52,13 +52,13 @@
h: none,
name: none,
name-anchor: "center",
ports: (),
ports-margins: (),
ports: (:),
ports-margins: (:),
fill: none,
stroke: black + 1pt,
id: "",
auto-ports: true,
ports-y: (),
ports-y: (:),
debug: (
ports: false
)
@ -88,15 +88,26 @@
if to-side in ports-margins {
margins = ports-margins.at(to-side)
}
let used-pct = 100% - margins.at(0) - margins.at(1)
let used-height = height * used-pct / 100%
let top-margin = height * margins.at(0) / 100%
let dy = used-height * (i + 1) / (ports.at(to-side).len() + 1)
if not auto-ports {
let dy
let top-margin
if to-side in ("east", "west") {
let used-pct = 100% - margins.at(0) - margins.at(1)
let used-height = height * used-pct / 100%
top-margin = height * margins.at(0) / 100%
dy = used-height * (i + 1) / (ports.at(to-side).len() + 1)
if not auto-ports {
top-margin = 0
dy = ports-y.at(to)(height)
}
} else if to-side == "north" {
dy = 0
top-margin = 0
} else if to-side == "south" {
dy = height
top-margin = 0
dy = ports-y.at(to)(height)
}
let (ctx, from-pos) = coordinate.resolve(ctx, from)

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@ -1,4 +1,4 @@
#import "@preview/cetz:0.2.2": draw
#import "@preview/cetz:0.3.2": draw
#import "element.typ"
#import "ports.typ": add-port
@ -71,7 +71,7 @@
let out-pct = if align-out {h-ratio / 2} else {50%}
let ports-y = (
"in": (h) => {h - h * (h-ratio / 200%)},
"out": (h) => {h * (out-pct / 100%)}
"out": (h) => {h - h * (out-pct / 100%)}
)
element.elmt(

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@ -1,4 +1,4 @@
#import "@preview/cetz:0.2.2": draw, coordinate
#import "@preview/cetz:0.3.2": draw, coordinate
#import "../util.typ"
/// Draws a group of elements

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@ -1,12 +1,12 @@
#import "@preview/cetz:0.2.2": draw
#import "@preview/cetz:0.3.2": draw
#import "gate.typ"
#let draw-shape(id, tl, tr, br, bl, fill, stroke) = {
let (x, y) = bl
let (width, height) = (tr.at(0) - x, tr.at(1) - y)
let t = (x + width / 4, y + height)
let b = (x + width / 4, y)
let t = (x + width / 2, y + height)
let b = (x + width / 2, y)
let f = draw.group(name: id, {
draw.merge-path(
@ -16,7 +16,7 @@
name: id + "-path",
close: true, {
draw.line(bl, tl, t)
draw.bezier((), b, tr, br)
draw.arc-through((), (tr , 50%, br), b)
draw.line((), b)
}
)

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@ -1,4 +1,4 @@
#import "@preview/cetz:0.2.2": draw
#import "@preview/cetz:0.3.2": draw
#import "gate.typ"
#let draw-shape(id, tl, tr, br, bl, fill, stroke) = {
@ -33,7 +33,7 @@
y: none,
w: none,
h: none,
inputs: 2,
inputs: 1,
fill: none,
stroke: black + 1pt,
id: "",
@ -65,7 +65,7 @@
y: none,
w: none,
h: none,
inputs: 2,
inputs: 1,
fill: none,
stroke: black + 1pt,
id: "",

View File

@ -1,4 +1,4 @@
#import "@preview/cetz:0.2.2": draw, coordinate
#import "@preview/cetz:0.3.2": draw, coordinate
#import "../ports.typ": add-ports, add-port
#import "../element.typ"
@ -33,7 +33,7 @@
stroke: black + 1pt,
id: "",
inverted: (),
inverted-radius: 0.2,
inverted-radius: 0.1,
debug: (
ports: false
)
@ -58,19 +58,16 @@
if (type(y) == dictionary) {
let from = y.from
let to = y.to
let (to-side, i) = find-port(ports, to)
let margins = (0%, 0%)
if to-side in ports-margins {
margins = ports-margins.at(to-side)
}
let used-pct = 100% - margins.at(0) - margins.at(1)
let used-height = height * used-pct / 100%
let top-margin = height * margins.at(0) / 100%
let dy = used-height * (i + 1) / (ports.at(to-side).len() + 1)
let dy
if to == "out" {
dy = height / 2
} else {
dy = height * (i + 0.5) / inputs
}
let (ctx, from-pos) = coordinate.resolve(ctx, from)
y = from-pos.at(1) + dy - height + top-margin
y = from-pos.at(1) + dy - height
}
let tl = (x, y + height)

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@ -0,0 +1,70 @@
#import "@preview/cetz:0.3.2": draw
// #import "iec_gate.typ" as iec-gate
#import "iec_gate.typ" as iec-gate
/// Draws an IEC-AND gate. This function is also available as `element.iec-gate-and()`
///
/// For parameters, see #doc-ref("gates.iec-gate")
/// #examples.iec-gate-and
#let iec-gate-and(
x: none,
y: none,
w: none,
h: none,
inputs: 2,
fill: none,
stroke: black + 1pt,
id: "",
inverted: (),
debug: (
ports: false
),
) = {
iec-gate.iec-gate(
x: x,
y: y,
w: w,
h: h,
inputs: inputs,
fill: fill,
stroke: stroke,
id: id,
inverted: inverted,
debug: debug,
symbol: $amp$,
)
}
/// Draws an IEC-NAND gate. This function is also available as `element.iec-gate-nand()`
///
/// For parameters, see #doc-ref("gates.iec-gate")
/// #examples.iec-gate-nand
#let iec-gate-nand(
x: none,
y: none,
w: none,
h: none,
inputs: 2,
fill: none,
stroke: black + 1pt,
id: "",
inverted: (),
debug: (
ports: false
),
) = {
iec-gate-and(
x: x,
y: y,
w: w,
h: h,
inputs: inputs,
fill: fill,
stroke: stroke,
id: id,
inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
debug: debug,
)
}

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@ -0,0 +1,68 @@
#import "@preview/cetz:0.3.2": draw
#import "iec_gate.typ" as iec-gate
/// Draws an IEC buffer gate. This function is also available as `element.iec-gate-buf()`
///
/// For parameters, see #doc-ref("gates.iec-gate")
/// #examples.iec-gate-buf
#let iec-gate-buf(
x: none,
y: none,
w: none,
h: none,
inputs: 2,
fill: none,
stroke: black + 1pt,
id: "",
inverted: (),
debug: (
ports: false,
),
) = {
iec-gate.iec-gate(
x: x,
y: y,
w: w,
h: h,
inputs: inputs,
fill: fill,
stroke: stroke,
id: id,
inverted: inverted,
debug: debug,
symbol: "1",
)
}
/// Draws an IEC NOT gate. This function is also available as `element.iec-gate-not()`
///
/// For parameters, see #doc-ref("gates.iec-gate")
/// #examples.iec-gate-not
#let iec-gate-not(
x: none,
y: none,
w: none,
h: none,
inputs: 2,
fill: none,
stroke: black + 1pt,
id: "",
inverted: (),
debug: (
ports: false,
),
) = {
iec-gate-buf(
x: x,
y: y,
w: w,
h: h,
inputs: inputs,
fill: fill,
stroke: stroke,
id: id,
inverted: if inverted != "all" { inverted + ("out",) } else { inverted },
debug: debug,
)
}

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@ -0,0 +1,125 @@
#import "@preview/cetz:0.3.2": draw, coordinate
#import "../ports.typ": add-ports, add-port
#import "../element.typ"
#let default-draw-shape(id, tl, tr, br, bl, fill, stroke, symbol) = {
let shapes = draw.rect(
inset: 0.5em,
fill: fill,
stroke: stroke,
name: id,
bl, tr
)
shapes += draw.content(
id + ".center",
[*$ symbol $*]
)
return (shapes, tl, tr, br, bl)
}
/// Draws a logic gate. This function is also available as `element.iec-gate()`
///
/// - draw-shape (function): see #doc-ref("element.elmt")
/// - x (number, dictionary): see #doc-ref("element.elmt")
/// - y (number, dictionary): see #doc-ref("element.elmt")
/// - w (number): see #doc-ref("element.elmt")
/// - h (number): see #doc-ref("element.elmt")
/// - inputs (int): The number of inputs
/// - fill (none, color): see #doc-ref("element.elmt")
/// - stroke (stroke): see #doc-ref("element.elmt")
/// - id (str): see #doc-ref("element.elmt")
/// - inverted (str, array): Either "all" or an array of port ids to display as inverted
/// - inverted-radius (number): The radius of inverted ports dot
/// - debug (dictionary): see #doc-ref("element.elmt")
/// - symbol (str): The symbol to display at the center of the gate
#let iec-gate(
draw-shape: default-draw-shape,
x: none,
y: none,
w: none,
h: none,
inputs: 2,
fill: none,
stroke: black + 1pt,
id: "",
inverted: (),
inverted-radius: 0.1,
debug: (
ports: false
),
symbol: "",
) = draw.get-ctx(ctx => {
let width = w
let height = h
let x = x
let y = y
if x == none { panic("Parameter x must be set") }
if y == none { panic("Parameter y must be set") }
if w == none { panic("Parameter w must be set") }
if h == none { panic("Parameter h must be set") }
if (type(x) == dictionary) {
let offset = x.rel
let to = x.to
let (ctx, to-pos) = coordinate.resolve(ctx, (rel: (offset, 0), to: to))
x = to-pos.at(0)
}
if (type(y) == dictionary) {
let from = y.from
let to = y.to
let dy
if to == "out" {
dy = height / 2
} else {
dy = height * (i + 0.5) / inputs
}
let (ctx, from-pos) = coordinate.resolve(ctx, from)
y = from-pos.at(1) + dy - height
}
let tl = (x, y + height)
let tr = (x + width, y + height)
let br = (x + width, y)
let bl = (x, y)
// Workaround because CeTZ needs to have all draw functions in the body
let func = {}
(func, tl, tr, br, bl) = draw-shape(id, tl, tr, br, bl, fill, stroke, symbol)
func
let space = 100% / inputs
for i in range(inputs) {
let pct = (i + 0.5) * space
let port-pos = (tl, pct, bl)
let port-name = "in" + str(i)
if inverted == "all" or port-name in inverted {
draw.circle(
port-pos,
radius: inverted-radius,
anchor: "east",
stroke: stroke
)
port-pos = (rel: (-2 * inverted-radius, 0), to: port-pos)
}
add-port(
id, "west",
(id: port-name), port-pos,
debug: debug.ports
)
}
let out-pos = id + ".east"
if inverted == "all" or "out" in inverted {
draw.circle(out-pos, radius: inverted-radius, anchor: "west", stroke: stroke)
out-pos = (rel: (2 * inverted-radius, 0), to: out-pos)
}
add-port(
id, "east",
(id: "out"), out-pos,
debug: debug.ports
)
})

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@ -0,0 +1,67 @@
#import "@preview/cetz:0.3.2": draw
#import "iec_gate.typ" as iec-gate
/// Draws an IEC-OR gate. This function is also available as `element.iec-gate-or()`
///
/// For parameters, see #doc-ref("gates.iec-gate")
/// #examples.iec-gate-or
#let iec-gate-or(
x: none,
y: none,
w: none,
h: none,
inputs: 2,
fill: none,
stroke: black + 1pt,
id: "",
inverted: (),
debug: (
ports: false
)
) = {
iec-gate.iec-gate(
x: x,
y: y,
w: w,
h: h,
inputs: inputs,
fill: fill,
stroke: stroke,
id: id,
inverted: inverted,
debug: debug,
symbol: $>= 1$,
)
}
/// Draws an IEC-NOR gate. This function is also available as `element.iec-gate-nor()`
///
/// For parameters, see #doc-ref("gates.iec-gate")
/// #examples.iec-gate-nor
#let iec-gate-nor(
x: none,
y: none,
w: none,
h: none,
inputs: 2,
fill: none,
stroke: black + 1pt,
id: "",
inverted: (),
debug: (
ports: false
)
) = {
iec-gate-or(
x: x,
y: y,
w: w,
h: h,
inputs: inputs,
fill: fill,
stroke: stroke,
id: id,
inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
debug: debug
)
}

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@ -0,0 +1,67 @@
#import "@preview/cetz:0.3.2": draw
#import "iec_gate.typ" as iec-gate
/// Draws an IEC-XOR gate. This function is also available as `element.iec-gate-xor()`
///
/// For parameters, see #doc-ref("gates.iec-gate")
/// #examples.iec-gate-xor
#let iec-gate-xor(
x: none,
y: none,
w: none,
h: none,
inputs: 2,
fill: none,
stroke: black + 1pt,
id: "",
inverted: (),
debug: (
ports: false
)
) = {
iec-gate.iec-gate(
x: x,
y: y,
w: w,
h: h,
inputs: inputs,
fill: fill,
stroke: stroke,
id: id,
inverted: inverted,
debug: debug,
symbol: $= 1$,
)
}
/// Draws an IEC-XNOR gate. This function is also available as `element.iec-gate-xnor()`
///
/// For parameters, see #doc-ref("gates.iec-gate")
/// #examples.iec-gate-xnor
#let iec-gate-xnor(
x: none,
y: none,
w: none,
h: none,
inputs: 2,
fill: none,
stroke: black + 1pt,
id: "",
inverted: (),
debug: (
ports: false
)
) = {
iec-gate-xor(
x: x,
y: y,
w: w,
h: h,
inputs: inputs,
fill: fill,
stroke: stroke,
id: id,
inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
debug: debug
)
}

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@ -1,4 +1,4 @@
#import "@preview/cetz:0.2.2": draw
#import "@preview/cetz:0.3.2": draw
#import "gate.typ"
#let draw-shape(id, tl, tr, br, bl, fill, stroke) = {

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@ -1,4 +1,4 @@
#import "@preview/cetz:0.2.2": draw
#import "@preview/cetz:0.3.2": draw
#import "gate.typ"
#let space = 10%

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@ -1,4 +1,4 @@
#import "@preview/cetz:0.2.2": draw
#import "@preview/cetz:0.3.2": draw
#import "../util.typ"
#import "element.typ"
#import "ports.typ": add-port

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@ -1,4 +1,4 @@
#import "@preview/cetz:0.2.2": draw
#import "@preview/cetz:0.3.2": draw
#import "../util.typ": rotate-anchor
#let add-port(

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@ -2,4 +2,9 @@
#import "elements/logic/and.typ": gate-and, gate-nand
#import "elements/logic/or.typ": gate-or, gate-nor
#import "elements/logic/xor.typ": gate-xor, gate-xnor
#import "elements/logic/buf.typ": gate-buf, gate-not
#import "elements/logic/buf.typ": gate-buf, gate-not
#import "elements/logic/iec_gate.typ": iec-gate
#import "elements/logic/iec_and.typ": iec-gate-and, iec-gate-nand
#import "elements/logic/iec_or.typ": iec-gate-or, iec-gate-nor
#import "elements/logic/iec_buf.typ": iec-gate-buf, iec-gate-not
#import "elements/logic/iec_xor.typ": iec-gate-xor, iec-gate-xnor

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@ -1,4 +1,4 @@
#let version = version((0,0,2))
#let version = version(0, 2, 0)
#import "circuit.typ": circuit
#import "element.typ"

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@ -1,4 +1,4 @@
#import "@preview/cetz:0.2.2": draw, coordinate
#import "@preview/cetz:0.3.2": draw, coordinate
#import "util.typ": opposite-anchor
/// List of valid wire styles
@ -7,7 +7,12 @@
#let signal-width = 1pt
#let bus-width = 1.5pt
#let intersection(pt, radius: .2, fill: black) = {
/// Draws a wire intersection at the given anchor
/// #examples.intersection
/// - pt (point): A CeTZ compatible point / anchor
/// - radius (number): The radius of the intersection
/// - fill (color): The fill color
#let intersection(pt, radius: .1, fill: black) = {
draw.circle(pt, radius: radius, stroke: none, fill: fill)
}
@ -192,15 +197,18 @@
let second-pos = points.at(1)
if reverse {
(first-pt, last-pt) = (last-pt, first-pt)
(first-pos, second-pos) = (second-pos, first-pos)
}
let angle = 0deg
if rotate-name {
(ctx, first-pos) = coordinate.resolve(ctx, first-pos)
(ctx, second-pos) = coordinate.resolve(ctx, second-pos)
let (x1, y1, _) = first-pos
let (x2, y2, _) = second-pos
if reverse {
(first-pos, second-pos) = (second-pos, first-pos)
}
let (x1, y1, ..) = first-pos
let (x2, y2, ..) = second-pos
angle = calc.atan2(x2 - x1, y2 - y1)
}

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@ -1,7 +1,7 @@
[package]
name = "circuiteria"
version = "0.0.2"
compiler = "0.11.0"
version = "0.2.0"
compiler = "0.13.0"
repository = "https://git.kb28.ch/HEL/circuiteria"
entrypoint = "src/lib.typ"
authors = [
@ -11,4 +11,4 @@ categories = [ "visualization" ]
license = "Apache-2.0"
description = "Drawing block circuits with Typst made easy, using CeTZ"
keywords = [ "circuit", "block", "draw" ]
exclude = [ "/gallery/*" ]
exclude = [ "gallery", "justfile", "doc" ]