Initial commit

Libs/Gates/hdl/and2_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF and2 IS
+BEGIN
+  out1 <= in1 and in2 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/and2inv1_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF and2inv1 IS
+BEGIN
+  out1 <= in1 and (not in2) after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/and2inv2_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF and2inv2 IS
+BEGIN
+  out1 <= (not in1) and (not in2) after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/and3_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF and3 IS
+BEGIN
+  out1 <= in1 and in2 and in3 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/and3inv1_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF and3inv1 IS
+BEGIN
+  out1 <= (not in1) and in2 and in3 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/and3inv2_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF and3inv2 IS
+BEGIN
+  out1 <= (not in1) and (not in2) and in3 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/and3inv3_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF and3inv3 IS
+BEGIN
+  out1 <= (not in1) and (not in2) and (not in3) after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/and4_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF and4 IS
+BEGIN
+  out1 <= in1 and in2 and in3 and in4 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/and4inv1_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF and4inv1 IS
+BEGIN
+  out1 <= (not in1) and in2 and in3 and in4 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/and4inv2_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF and4inv2 IS
+BEGIN
+  out1 <= (not in1) and (not in2) and in3 and in4 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/and4inv3_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF and4inv3 IS
+BEGIN
+  out1 <= (not in1) and (not in2) and (not in3) and in4 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/and4inv4_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF and4inv4 IS
+BEGIN
+  out1 <= (not in1) and (not in2) and (not in3) and (not in4) after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/and5_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF and5 IS
+BEGIN
+  out1 <= in1 and in2 and in3 and in4 and in5 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/bufferLogicVector_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF bufferLogicVector IS
+BEGIN
+  out1 <= in1 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/bufferSigned_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF bufferSigned IS
+BEGIN
+  out1 <= in1 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/bufferULogicVector_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF bufferUlogicVector IS
+BEGIN
+  out1 <= in1 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/bufferULogic_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF bufferUlogic IS
+BEGIN
+  out1 <= in1 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/bufferUnsigned_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF bufferUnsigned IS
+BEGIN
+  out1 <= in1 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/demux1to2_sim.vhd

@@ -0,0 +1,19 @@
+ARCHITECTURE sim OF demux1to2 IS
+BEGIN
+
+  process(sel, in1)
+  begin
+    -- default values
+    out0 <= '0';
+    out1 <= '0';
+
+    -- selection
+    case sel is
+      when '0' => out0 <= in1 after delay;
+      when '1' => out1 <= in1 after delay;
+      when others => NULL;
+    end case;
+
+  end process;
+
+END ARCHITECTURE sim;

Libs/Gates/hdl/demux1to4_sim.vhd

@@ -0,0 +1,23 @@
+ARCHITECTURE sim OF demux1to4 IS
+BEGIN
+
+  process(sel, in1)
+  begin
+    -- default values
+    out0 <= '0';
+    out1 <= '0';
+    out2 <= '0';
+    out3 <= '0';
+
+    -- selection
+    case sel is
+      when "00" => out0 <= in1 after delay;
+      when "01" => out1 <= in1 after delay;
+      when "10" => out2 <= in1 after delay;
+      when "11" => out3 <= in1 after delay;
+      when others => NULL;
+    end case;
+
+  end process;
+
+END ARCHITECTURE sim;

Libs/Gates/hdl/gates_pkg.vhd

@@ -0,0 +1,9 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+PACKAGE gates IS
+
+--  constant gateDelay: time := 1 ns;
+  constant gateDelay: time := 0.1 ns;
+
+END gates;

Libs/Gates/hdl/inverter_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF inverter IS
+BEGIN
+  out1 <= NOT in1 after delay;
+END sim;

Libs/Gates/hdl/logic0_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF logic0 IS
+BEGIN
+  logic_0 <= '0';
+END sim;

Libs/Gates/hdl/logic1_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF logic1 IS
+BEGIN
+  logic_1 <= '1';
+END sim;

Libs/Gates/hdl/mux16to1_sim.vhd

@@ -0,0 +1,33 @@
+ARCHITECTURE sim OF mux16to1 IS
+
+BEGIN
+
+  P1: process(sel,
+              in0, in1, in2, in3,
+              in4, in5, in6, in7,
+              in8, in9, in10, in11,
+              in12, in13, in14, in15
+             )
+  begin
+    case to_integer(sel) is
+      when  0 => muxOut <=  in0 after delay;
+      when  1 => muxOut <=  in1 after delay;
+      when  2 => muxOut <=  in2 after delay;
+      when  3 => muxOut <=  in3 after delay;
+      when  4 => muxOut <=  in4 after delay;
+      when  5 => muxOut <=  in5 after delay;
+      when  6 => muxOut <=  in6 after delay;
+      when  7 => muxOut <=  in7 after delay;
+      when  8 => muxOut <=  in8 after delay;
+      when  9 => muxOut <=  in9 after delay;
+      when 10 => muxOut <= in10 after delay;
+      when 11 => muxOut <= in11 after delay;
+      when 12 => muxOut <= in12 after delay;
+      when 13 => muxOut <= in13 after delay;
+      when 14 => muxOut <= in14 after delay;
+      when 15 => muxOut <= in15 after delay;
+      when others => null;
+    end case;
+  end process P1;
+
+END ARCHITECTURE sim;

Libs/Gates/hdl/mux2to1Signed_sim.vhd

@@ -0,0 +1,22 @@
+ARCHITECTURE sim OF mux2to1Signed IS
+
+  signal selInt: std_ulogic;
+
+BEGIN
+
+  selInt <= to_X01(sel);
+
+  muxSelect: process(selInt, in0, in1)
+  begin
+    if selInt = '0' then
+      muxOut <= in0 after delay;
+    elsif selInt = '1' then
+      muxOut <= in1 after delay;
+    elsif in0 = in1 then
+      muxOut <= in0 after delay;
+    else
+      muxOut <= (others => 'X') after delay;
+    end if;
+  end process muxSelect;
+
+END ARCHITECTURE sim;

Libs/Gates/hdl/mux2to1ULogicVector_sim.vhd

@@ -0,0 +1,22 @@
+ARCHITECTURE sim OF mux2to1ULogicVector IS
+
+  signal selInt: std_ulogic;
+
+BEGIN
+
+  selInt <= to_X01(sel);
+
+  muxSelect: process(selInt, in0, in1)
+  begin
+    if selInt = '0' then
+      muxOut <= in0 after delay;
+    elsif selInt = '1' then
+      muxOut <= in1 after delay;
+    elsif in0 = in1 then
+      muxOut <= in0 after delay;
+    else
+      muxOut <= (others => 'X') after delay;
+    end if;
+  end process muxSelect;
+
+END ARCHITECTURE sim;

Libs/Gates/hdl/mux2to1Unsigned_sim.vhd

@@ -0,0 +1,22 @@
+ARCHITECTURE sim OF mux2to1Unsigned IS
+
+  signal selInt: std_ulogic;
+
+BEGIN
+
+  selInt <= to_X01(sel);
+
+  muxSelect: process(selInt, in0, in1)
+  begin
+    if selInt = '0' then
+      muxOut <= in0 after delay;
+    elsif selInt = '1' then
+      muxOut <= in1 after delay;
+    elsif in0 = in1 then
+      muxOut <= in0 after delay;
+    else
+      muxOut <= (others => 'X') after delay;
+    end if;
+  end process muxSelect;
+
+END ARCHITECTURE sim;

Libs/Gates/hdl/mux2to1_sim.vhd

@@ -0,0 +1,43 @@
+ARCHITECTURE sim OF mux2to1 IS
+  subtype tSelect is std_uLogic_vector(0 to 2);
+BEGIN
+
+  muxSelect: process(sel, in0, in1)
+  begin
+    if sel = '1' then
+        muxOut <= in1 after delay;
+    elsif sel = '0' then
+        muxOut <= in0 after delay;
+    else
+    	muxOut <= 'X' after delay;
+    end if;
+  end process muxSelect;
+
+-- muxSelect: process(sel, in0, in1)
+--  begin
+--   -- case tSelect'(to_X01(sel & in0 & in1)) is
+--    case to_X01(tSelect'(sel & in0 & in1)) is
+--      -- select in0
+--      when "000" => muxOut <= '0' after delay;
+--      when "001" => muxOut <= '0' after delay;
+--      when "00X" => muxOut <= '0' after delay;
+--      when "010" => muxOut <= '1' after delay;
+--      when "011" => muxOut <= '1' after delay;
+--      when "01X" => muxOut <= '1' after delay;
+--      -- select in1
+--      when "100" => muxOut <= '0' after delay;
+--      when "110" => muxOut <= '0' after delay;
+--      when "1X0" => muxOut <= '0' after delay;
+--      when "101" => muxOut <= '1' after delay;
+--      when "111" => muxOut <= '1' after delay;
+--      when "1X1" => muxOut <= '1' after delay;
+--      -- select in0 equal to in1
+--      when "X00" => muxOut <= '0' after delay;
+--      when "X11" => muxOut <= '1' after delay;
+--      -- others
+--      when others => muxOut <= 'X' after delay;
+--    end case;
+--  end process muxSelect;
+
+
+END ARCHITECTURE sim;

Libs/Gates/hdl/mux4to1Signed_sim.vhd

@@ -0,0 +1,16 @@
+ARCHITECTURE sim OF mux4to1Signed IS
+
+BEGIN
+
+  muxSelect: process(sel, in0, in1, in2, in3)
+  begin
+    case to_integer(sel) is
+      when 0 => muxOut <= in0 after delay;
+      when 1 => muxOut <= in1 after delay;
+      when 2 => muxOut <= in2 after delay;
+      when 3 => muxOut <= in3 after delay;
+      when others => muxOut <= (others => 'X') after delay;
+    end case;
+  end process muxSelect;
+
+END ARCHITECTURE sim;

Libs/Gates/hdl/mux4to1ULogicVector_sim.vhd

@@ -0,0 +1,16 @@
+ARCHITECTURE sim OF mux4to1ULogicVector IS
+
+BEGIN
+
+  muxSelect: process(sel, in0, in1, in2, in3)
+  begin
+    case to_integer(sel) is
+      when 0 => muxOut <= in0 after delay;
+      when 1 => muxOut <= in1 after delay;
+      when 2 => muxOut <= in2 after delay;
+      when 3 => muxOut <= in3 after delay;
+      when others => muxOut <= (others => 'X') after delay;
+    end case;
+  end process muxSelect;
+
+END ARCHITECTURE sim;

Libs/Gates/hdl/mux4to1Unsigned_sim.vhd

@@ -0,0 +1,16 @@
+ARCHITECTURE sim OF mux4to1Unsigned IS
+
+BEGIN
+
+  muxSelect: process(sel, in0, in1, in2, in3)
+  begin
+    case to_integer(sel) is
+      when 0 => muxOut <= in0 after delay;
+      when 1 => muxOut <= in1 after delay;
+      when 2 => muxOut <= in2 after delay;
+      when 3 => muxOut <= in3 after delay;
+      when others => muxOut <= (others => 'X') after delay;
+    end case;
+  end process muxSelect;
+
+END ARCHITECTURE sim;

Libs/Gates/hdl/mux4to1_sim.vhd

@@ -0,0 +1,16 @@
+ARCHITECTURE sim OF mux4to1 IS
+
+BEGIN
+
+  muxSelect: process(sel, in0, in1, in2, in3)
+  begin
+    case to_integer(sel) is
+      when 0 => muxOut <= in0 after delay;
+      when 1 => muxOut <= in1 after delay;
+      when 2 => muxOut <= in2 after delay;
+      when 3 => muxOut <= in3 after delay;
+      when others => muxOut <= 'X' after delay;
+    end case;
+  end process muxSelect;
+
+END ARCHITECTURE sim;

Libs/Gates/hdl/nand2_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF nand2 IS
+BEGIN
+  out1 <= not( in1 and in2 ) after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/nor2_m_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF nor2_m IS
+BEGIN
+  out1 <= (not in1) and (not in2) after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/nor2_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF nor2 IS
+BEGIN
+  out1 <= not( in1 or in2 ) after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/onesSigned_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF onesSigned IS
+BEGIN
+  ones <= (others => '1');
+END sim;

Libs/Gates/hdl/onesUnsigned_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF onesUnsigned IS
+BEGIN
+  ones <= (others => '1');
+END sim;

Libs/Gates/hdl/or2_m_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF or2_m IS
+BEGIN
+  out1 <= in1 or in2 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/or2_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF or2 IS
+BEGIN
+  out1 <= in1 or in2 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/or2inv1_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF or2inv1 IS
+BEGIN
+  out1 <= (not in1) or in2 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/or2inv2_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF or2inv2 IS
+BEGIN
+  out1 <= (not in1) or (not in2) after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/or3_m_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF or3_m IS
+BEGIN
+  out1 <= in1 or in2 or in3 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/or3_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF or3 IS
+BEGIN
+  out1 <= in1 or in2 or in3 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/or4_m_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF or4_m IS
+BEGIN
+  out1 <= in1 or in2 or in3 or in4 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/or4_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF or4 IS
+BEGIN
+  out1 <= in1 or in2 or in3 or in4 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/or5_m_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF or5_m IS
+BEGIN
+  out1 <= in1 or in2 or in3 or in4 or in5 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/or5_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF or5 IS
+BEGIN
+  out1 <= in1 or in2 or in3 or in4 or in5 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/transLogUlog_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF transLogUlog IS
+BEGIN
+  out1 <= std_ulogic_vector(in1) after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/transSignedUlog_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF transSignedUlog IS
+BEGIN
+  out1 <= std_ulogic_vector(in1) after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/transSignedUnsigned_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF transSignedUnsigned IS
+BEGIN
+  out1 <= unsigned(in1) after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/transUlogSigned_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF transUlogSigned IS
+BEGIN
+  out1 <= signed(in1) after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/transUlogUnsigned_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF transUlogUnsigned IS
+BEGIN
+  out1 <= unsigned(in1) after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/transUnsignedSigned_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF transUnsignedSigned IS
+BEGIN
+  out1 <= signed(in1) after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/transUnsignedUlog_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF transUnsignedUlog IS
+BEGIN
+  out1 <= std_ulogic_vector(in1) after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/xnor2_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF xnor2 IS
+BEGIN
+  xorOut <= not in1 xor in2 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/xor2_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF xor2 IS
+BEGIN
+  xorOut <= in1 xor in2 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/xor3_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF xor3 IS
+BEGIN
+  xorOut <= in1 xor in2 xor in3 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/xor4_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF xor4 IS
+BEGIN
+  xorOut <= in1 xor in2 xor in3 xor in4 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/xor5_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF xor5 IS
+BEGIN
+  xorOut <= in1 xor in2 xor in3 xor in4 xor in5 after delay;
+END ARCHITECTURE sim;

Libs/Gates/hdl/zeroSigned_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF zeroSigned IS
+BEGIN
+  zero <= (others => '0');
+END sim;

Libs/Gates/hdl/zeroUnsigned_sim.vhd

@@ -0,0 +1,4 @@
+ARCHITECTURE sim OF zeroUnsigned IS
+BEGIN
+  zero <= (others => '0');
+END sim;

Libs/Gates/hds/.hdlsidedata/_and2_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

Libs/Gates/hds/.hdlsidedata/_and2_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and2_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and2inv1_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and2inv1_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and2inv2_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and2inv2_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and3_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_ANY

Libs/Gates/hds/.hdlsidedata/_and3_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and3_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and3inv1_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and3inv1_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and3inv2_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and3inv2_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and3inv3_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and3inv3_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and4_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and4_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and4inv1_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and4inv1_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and4inv2_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and4inv2_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and4inv3_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and4inv3_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and4inv4_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and4inv4_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and5_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_and5_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_bufferLogicVector_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_bufferSigned_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_bufferULogicVector_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_bufferULogic_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_bufferUnsigned_sim.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_bufferlogicvector_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_buffersigned_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_bufferulogic_entity.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_bufferulogic_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/Gates/hds/.hdlsidedata/_bufferulogicvector_entity.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008